DS1339U-33+T&R Maxim Integrated Products, DS1339U-33+T&R Datasheet - Page 16

• Manufacturer Part Number: DS1339U-33+T&R
• Description: IC RTC I2C W/ALARM 8-USOP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Alarmr

Specifications of DS1339U-33+T&R

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Figure 5. Programmable Trickle Charger
I
The DS1339 supports the I
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339
operates as a slave on the I
mode (400kHz cycle rate) are defined. The DS1339 works in both modes. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined
Accordingly, the following bus conditions have been defined:
2
C SERIAL DATA BUS
V
TCS3
CC


BIT 7
NOTE: ONLY 1010 ENABLES CHARGER
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is HIGH are interpreted as control signals.
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during
the LOW period of the clock signal. There is one clock pulse per bit of data.
1 OF 16 SELECT
TCS2
BIT 6
TRICKLE CHARGE REGISTER
TCS1
BIT 5
2
C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
2
C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast
TCS0
BIT 4
BIT 3
DS1
SELECT
1 OF 2
(Figure
BIT 2
DS0
6):
16 of 20
ROUT1
BIT 1
SELECT
1 OF 3
ROUT0
BIT 0
TCS
DS
ROUT
DS1339 I
0-1
0-3
0-1
= DIODE SELECT
= TRICKLE CHARGER SELECT
= RESISTOR SELECT
2
C Serial Real-Time Clock
250
2k
4k
R1
R2
R3
V
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