DS1339U-33+T&R Maxim Integrated Products, DS1339U-33+T&R Datasheet - Page 5

• Manufacturer Part Number: DS1339U-33+T&R
• Description: IC RTC I2C W/ALARM 8-USOP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Alarmr

Specifications of DS1339U-33+T&R

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

POWER-UP/DOWN CHARACTERISTICS
(T
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Figure 1. Power-Up/Down Timing
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Recovery at Power-Up
V
V
A
CC
CC
= -40C to +85°C) (Note 1,
V
OUTPUTS
V
Fall Time; V
Rise Time; V
PF(MAX)
PF(MIN)
INPUTS
V
CC
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA and SQW/INT.
I
Specified with the I
V
Using recommended crystal on X1 and X2.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
the undefined region of the falling edge of SCL.
The maximum t
A fast-mode device can be used in a standard-mode system, but the requirement t
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
is released.
C
Guaranteed by design. Not production tested.
The parameter t
V
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
CCA
CC
B
CC
PARAMETER
—total capacitance of one bus line in pF.
—SCL at f
must be less than 3.63V if the 250 resistor is selected.
 V
CCMAX
PF(MAX)
PF(MIN)
RECOGNIZED
VALID
and 1.3V  V
SC
HD:DAT
OSF
max, V
to V
to V
2
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V 
C bus inactive, V
t
VCCF
need only be met if the device does not stretch the LOW period (t
PF(MIN)
PF(MAX)
IL
= 0.0V, V
Figure
BACKUP
 3.7V.
1)
IH
IL
= V
SYMBOL
= 0.0V, V
t
t
CC
t
VCCR
VCCF
REC
, trickle charger disabled.
IH
= V
(Note 15)
CC
5 of 20
, trickle charger disabled.
CONDITIONS
DON'T CARE
HIGH-Z
R(MAX)
+ t
SU:DAT
SU:DAT
MIN
300
DS1339 I
0
= 1000 + 250 = 1250ns before the SCL line
LOW
 to 250ns must then be met. This is
) of the SCL signal.
TYP
IHMIN
2
C Serial Real-Time Clock
of the SCL signal) to bridge
t
VCCR
MAX
2
RECOGNIZED
t
REC
VALID
UNITS
ms
s
s