DS1643P-100+ Maxim Integrated Products, DS1643P-100+ Datasheet - Page 5

• Manufacturer Part Number: DS1643P-100+
• Description: IC RAM TIMEKEEP NV 100NS 34-PCM
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS1643P-100+

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 34-PowerCap™ Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within 1 minute per month at 25C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within 1.53 minutes per month (35ppm) at 25C.
Table 2. Register Map—Bank1
Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
and
available at the latter of chip enable access (t
data input/output pins (DQ) is controlled by
lines are driven to an intermediate state until t
remain valid, output data will remain valid for output data hold time (t
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever
referenced to the latter occurring transition of
the cycle.
write cycle. Data in must be valid t
typical application, the
that care is taken with the data bus to avoid bus contention. If
the data bus can become active with read data defined by the address inputs. A low transition on
then disable the outputs t
OSC = STOP BIT
W = WRITE BIT
ADDRESS
1FFD
1FFC
1FFB
1FFA
1FFE
1FFF
1FF9
1FF8
OE
access times and states are satisfied. If
CE
or
OSC
B
—
W
X
X
X
X
X
WE
7
must return inactive for a minimum of t
OE
WEZ
B
—
—
—
Ft
X
X
X
R
R = READ BIT
X = UNUSED
6
signal will be high during a write cycle. However,
after
B
—
—
—
—
—
X
X
X
WE
5
DS
goes active.
prior to the end of write and remain valid for t
B
—
—
—
—
—
—
X
X
4
DATA
WE
AA
CE
CEA
WE
FT = FREQUENCY TEST
after the last address input is stable, providing that the
WE
AA
) or at output enable access time (t
(write enable) is high and
and
B
—
—
—
—
—
—
CE
X
X
5 of 17
. If the address inputs are changed while
and
3
or
or
OE
CE
CE
OE
. If the outputs are activated before t
B
—
—
—
—
—
—
—
X
. The addresses must be held valid throughout
are in their active state. The start of a write is
2
access times are not met, valid data will be
WR
OE
B
—
—
—
—
—
—
—
prior to the initiation of another read or
X
1
is low prior to
OH
) but will then go indeterminate
B
—
—
—
—
—
—
—
X
0
CE
OE
(chip enable) is low. The
FUNCTION
Seconds
can be active provided
Minutes
Control
Month
WE
OEA
Hour
Year
Date
Day
). The state of the
DH
transitioning low
DS1643/DS1643P
afterward. In a
CE
AA
, the data
RANGE
WE
and
00-99
01-12
01-31
01-07
00-23
00-59
00-59
A
will
CE
OE