DS14285Q Maxim Integrated Products, DS14285Q Datasheet - Page 15

• Manufacturer Part Number: DS14285Q
• Description: IC RTC W/NV RAM CNTRL 28-PLCC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS14285Q

• Memory Size: 114B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-LCC, 28-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency
UPDATE CYCLE
The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and
alarm bytes is frozen and will not update as the time increments. However, the time countdown chain
continues to update the internal copy of the buffer. This feature allows time to maintain accuracy
independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and
calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 µs.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 4). Periodic interrupts
that occur at a rate of greater than t
occurrence of the periodic interrupt. The reads should be complete within 1 (t
data is not read during the update cycle.
RS3
SELECT BITS REGISTER A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BUC
allow valid time and date information to be reached at each
INTERRUPT RATE
t
PI
1.953125ms
976.5625µs
3.90625ms
3.90625ms
122.070µs
244.141µs
488.281µs
7.8125ms
7.8125ms
15.625ms
PERIODIC
31.25ms
15 of 26
62.5ms
125ms
250ms
500ms
None
PI/
SQW OUTPUT
FREQUENCY
2
8.192kHz
4.096kHz
2.048kHz
1.024kHz
+ t
256Hz
128Hz
512Hz
256Hz
128Hz
None
64Hz
32Hz
16Hz
8Hz
4Hz
2Hz
BUC
) to ensure that