DS14285Q Maxim Integrated Products, DS14285Q Datasheet - Page 3

• Manufacturer Part Number: DS14285Q
• Description: IC RTC W/NV RAM CNTRL 28-PLCC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS14285Q

• Memory Size: 114B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-LCC, 28-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS14285/DS14287
DETAILED DESCRIPTION
The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287
clock function with the additional feature of providing nonvolatile control for an external SRAM.
Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt,
square wave generator, and 114 bytes of nonvolatile static RAM. For the DS14287 a lithium energy
source, quartz crystal, and write protection circuitry are contained within a 24-pin dual in-line package.
The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external
energy source connected to the V
pin. A standard 32.768 kHz quartz crystal can be directly connected
BAT
to the DS14285 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load
capacitance (C
) of 6 pF. For more information on crystal selection and crystal layout considerations,
L
please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.”
The DS14285/DS14287 uses its backup energy source and battery-backup controller to make a standard
CMOS static RAM nonvolatile during power-fail conditions. During power fail, the DS14285/DS14287
automatically write-protects the external SRAM and provides a V
output sourced from its internal
CC
battery.
For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when
shipped from the factory. This isolation is removed after the first application of V
allowing the lithium
CC,
cell to provide data retention to the clock, internal RAM, V
and
on subsequent power-downs.
CEO
CCO
Care must be taken after this isolation has been broken to avoid inadvertently discharging the lithium cell
through the V
and
pins.
CEO
CCO
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS14285/DS14287. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, V
- DC power is provided to the device on these pins. V
is the +5 volt input.
CC
CC
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15
internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE
bit in Register B. The SQW signal is not available when V
is less than 4.25 volts typical.
CC
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287
since the bus change from address to data occurs during the internal RAM access time. Addresses must be
valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from
AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or
WR
pulses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or
pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions
RD
low in the case of Motorola timing or as
transitions high in the case of Intel timing.
RD
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