AD73311LARU Analog Devices Inc, AD73311LARU Datasheet - Page 12

• Manufacturer Part Number: AD73311LARU
• Description: IC ANALOG FRONT END 20-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73311LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-TSSOP
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Not Compliant

AD73311L
SPORT Register Maps
There are two register banks for the AD73311L: the control
register bank and the data register bank. The control register
bank consists of six read/write registers, each eight bits wide.
Table IX shows the control register map for the AD73311L.
The first two control registers, CRA and CRB, are reserved for
controlling the SPORT. They hold settings for parameters such
as bit rate, internal master clock rate and device count (used
when more than one AD73311L is connected in cascade from
a single SPORT). The other three registers; CRC, CRD and
CRE are used to hold control settings for the ADC, DAC,
Reference and Power Control sections of the device. Control
registers are written to on the negative edge of SCLK. The
data register bank consists of two 16-bit registers that are the
DAC and ADC registers.
Master Clock Divider
The AD73311L features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to
produce an internal master clock signal (DMCLK) that is used
to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table V shows
the division ratio corresponding to the various bit settings. The
default divider ratio is divide-by-one.
MCD2
0
0
0
0
1
1
1
1
Serial Clock Rate Divider
The AD73311L features a programmable serial clock divider that
allows users to match the serial clock (SCLK) rate of the data to
that of the DSP engine or host processor. The maximum SCLK
rate available is DMCLK and the other available rates are:
DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
Table V. DMCLK (Internal) Rate Divider Settings
MCD1
0
0
1
1
0
0
1
1
REGISTER A
CONTROL
MCLK
(EXTERNAL)
SE
RESET
SDIFS
SDI
MCD0
0
1
0
1
0
1
0
1
8
REGISTER B
CONTROL
3
DIVIDER
MCLK
DMCLK
(INTERNAL)
DMCLK Rate
MCLK
MCLK/2
MCLK/3
MCLK/4
MCLK/5
MCLK
MCLK
MCLK
8
REGISTER C
CONTROL
SERIAL REGISTER
SERIAL REGISTER
8
SERIAL PORT
(SPORT)
8
is programmable by setting bits CRB:2–3. Table VI shows the
serial clock rate corresponding to the various bit settings.
Sample Rate Divider
The AD73311L features a programmable sample rate divider
that allows users flexibility in matching the codec’s ADC and
DAC sample rates to the needs of the DSP software. The maxi-
mum sample rate available is DMCLK/256 which offers the
lowest conversion group delay, while the other available rates
are: DMCLK/512, DMCLK/1024 and DMCLK/2048. The
slowest rate (DMCLK/2048) is the default sample rate. The
sample rate divider is programmable by setting bits CRB:0-1.
Table VII shows the sample rate corresponding to the various
bit settings.
DAC Advance Register
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(DMCLK/8); see Table VIII. In certain
circumstances this can reduce the group delay when the ADC
and DAC are used to process data in series. Appendix E details
how the DAC advance feature can be used.
NOTE: The DAC advance register should be changed before
the DAC section is powered up.
REGISTER D
CONTROL
SCD1
0
0
1
1
DIR1
0
0
1
1
Table VII. Sample Rate Divider Settings
Table VI. SCLK Rate Divider Settings
DIVIDER
2
SCLK
8
REGISTER E
8
CONTROL
DIR0
0
1
0
1
SCD0
0
1
0
1
SDOFS
SCLK
SDO
SCLK Rate
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
SCLK Rate
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
REGISTER F
CONTROL