AD73311LARU Analog Devices Inc, AD73311LARU Datasheet - Page 3

• Manufacturer Part Number: AD73311LARU
• Description: IC ANALOG FRONT END 20-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73311LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-TSSOP
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Not Compliant

Parameter
DAC SPECIFICATIONS (Continued)
FREQUENCY RESPONSE
LOGIC INPUTS
LOGIC OUTPUT
POWER SUPPLIES
NOTES
10
Specifications subject to change without notice.
Conditions
ADC Only On
ADC and DAC On 5.6
REFCAP Only On
REFCAP and
All Sections Off
All Sections Off
The above values are in mA and are typical values unless otherwise noted.
1
2
3
4
5
6
7
8
9
Operating temperature range is as follows: –40°C to +105°C. Therefore, T
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
At input to sigma-delta modulator of ADC.
Guaranteed by design.
Overall group delay will be affected by the sample rate and the external digital filtering.
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 10
Between VOUTP and VOUTN.
At VOUT output.
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
REFOUT Only On 2.7
Power Supply Rejection
Group Delay
Output DC Offset
Minimum Load Resistance, R
Maximum Load Capacitance, C
(ADC AND DAC)
V
V
I
C
V
V
Three-State Leakage Current
AVDD1, AVDD2
DVDD
I
IH
DD
INH
INL
OH
OL
IN
Single-Ended
Differential
Single-Ended
Differential
0
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
> 0.5
, Input Current
10
, Input Capacitance
, Output Low Voltage
, Output High Voltage
, Input Low Voltage
, Input High Voltage
4, 5
2, 7
9
Analog
Current Current
2
0.65
0
1 µA
Typical Output
L
Internal Digital External Interface
4.5
4.8
0.6
0.5 µA
0
0
2, 8
L
2, 8
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Min
–30
150
150
V
0
V
0
–10
2.7
2.7
DD
DD
Current
0.5
0.5
0
0
0
0
– 0.8
– 0.4
AD73311LA
MIN
Typ
–81
25
+5
0
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
= –40°C and T
Max
+50
500
100
V
0.8
10
10
V
0.4
+10
3.3
3.3
DD
DD
Total Current
(Max)
8.0
12.5
1.0
3.8
0.75
20 µA
MAX
11
= +105°C.
)/DMCLK.
Unit
dB
µs
mV
Ω
Ω
pF
pF
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
V
µA
pF
V
V
µA
V
V
SE
1
1
0
0
0
0
Test Conditions/Comments
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
PGA = 6 dB
Normalized to f
Channel Frequency Response Is
Programmable by Means of External
Digital Filtering
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
See Table I
MCLK
ON
YES
YES
NO
NO
YES
NO
Comments
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
MCLK Active Levels Equal to
0 V and DVDD
Digital Inputs Static and Equal
to 0 V or DVDD
SAMP
AD73311L