AD73322AR Analog Devices Inc, AD73322AR Datasheet - Page 6

• Manufacturer Part Number: AD73322AR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322AR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

AD73322
P
DIGITAL GAIN TAP
DAC SPECIFICATIONS
FREQUENCY RESPONSE
arameter
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
Maximum Voltage Output Swing
Nominal Voltage Output Swing (0 dBm0)
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
Total Harmonic Distortion at 0 dBm0
Intermodulation Distortion
Idle Channel Noise
Crosstalk
Power Supply Rejection
Group Delay
Output DC Offset
Minimum Load Resistance, R
Maximum Load Capacitance, C
(ADC and DAC)
Frequency (Normalized to FS)
Single-Ended
Differential
Single-Ended
Differential
PGA = 6 dB
PGA = 6 dB
Single-Ended
Differential
Single-Ended
Differential
0
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
> 0.5
DAC-to-ADC
DAC-to-DAC
4, 5
9
2, 7
Typical Output
L
2, 8
L
2
2, 8
Min
150
150
AD73322A
Typ
–1
16
25
3.156
3.17
6.312
9.19
2.1908
0
4.3918
6.02
2.4
77
–80
–90
–77
–100
–65
25
50
+12
0
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
+1
100
+0.4
–85
–85
0.1
–6–
Max
500
100
Units
V
V
Bits
V p-p
dBm
V p-p
dBm
V p-p
dBm
V p-p
dBm
V
dB
dB
dB
dB
dB
dBm0
dB
dB
dB
dB
mV
pF
pF
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
s
s
s
s
PGA = 6 dB
PGA = 6 dB
PGA = 6 dB
PGA = 6 dB
ADC Input Signal Level: AGND; DAC
DAC1 Output Signal Level: AGND; DAC2
Test Conditions/Comments
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
5VEN = 1
Max Output = (3.156/2.4) VREFCAP
Max Output = 2 ([3.156/2.4] VREFCAP)
REFOUT Unloaded
1.0 kHz, 0 dBm0; Unloaded
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 8
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
PGA = 0 dB
PGA = 0 dB
Output Signal Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
Input Amplifiers Included In Input Channel
Output Signal Level: 1.0 kHz, 0 dBm0
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Interpolator Bypassed
SAMP
SAMP
= 64 kHz
= 64 kHz
REV. B