AD73322AR Analog Devices Inc, AD73322AR Datasheet - Page 8

• Manufacturer Part Number: AD73322AR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322AR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

VREFCAP
VREFOUT
ADC
DAC
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
Specifications subject to change without notice.
AD73322
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
Maximum Input Range
Nominal Reference Level
Maximum Voltage
Output Swing
Nominal Voltage
Output Swing
Output Bias Voltage
at V
Single-Ended
Differential
Single-Ended
Differential
IN
Limit at
T
61
24.4
24.4
t
0.4
0.4
20
0
10
10
10
10
30
1
A
= –40 C to +85 C
t
t
1
1
(AVDD = +3 V
otherwise noted)
3 V Power Supply
5VEN = 0
1.2 V
1.2 V
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
Table III. Signal Ranges
10%; DVDD = +3 V
10%
10%
–8–
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
5VEN = 0
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
1.2 V
1.2 V
VREFOUT
10%; AGND = DGND = 0 V; T
5 V Power Supply
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
A
= T
5VEN = 1
MlN
3.156 V p-p
6.312 V p-p
2.1908 V p-p
4.3818 V p-p
2.4 V
2.4 V
3.156 V p-p
2.1908 V p-p
VREFOUT
to T
MAX
, unless
REV. B