MCP3001-I/SN Microchip Technology, MCP3001-I/SN Datasheet - Page 15

• Manufacturer Part Number: MCP3001-I/SN
• Description: IC ADC 10BIT 2.7V 1CH SPI 8-SOIC
• Manufacturer: Microchip Technology

Specifications of MCP3001-I/SN

• Data Interface: Serial, SPI™
• Number Of Bits: 10
• Sampling Rate (per Second): 200k
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Resolution (bits): 10bit
• Sampling Rate: 200kSPS
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 400µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.0
Communication with the device is done using a stan-
dard SPI compatible serial interface. Initiating commu-
nication with the MCP3001 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate commu-
nication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 10 clocks will output the result of the conver-
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 10 data bits have been transmitted and the
FIGURE 5-1:
FIGURE 5-2:
© 2007 Microchip Technology Inc.
D
SERIAL COMMUNICATIONS
CLK
CS
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data,
followed by zeros indefinitely. See Figure below.
** t
high impedance node.
OUT
D
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefi-
nitely.
** t
high impedance node leaving the CLK running to clock out the LSB-first data or zeros.
CLK
CS
OUT
DATA
DATA
Communication with MCP3001 (MSB first Format).
Communication with MCP3001 (LSB first Format).
: during this time, the bias current and the comparator powers down and the reference input becomes a
t
SAMPLE
: during this time, the bias current and the comparator powers down and the reference input becomes a
HI-Z
HI-Z
t
SAMPLE
t
SUCS
t
SUCS
NULL
BIT
NULL
BIT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
t
CONV
t
CONV
t
CYC
t
CYC
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
If it is desired, the CS can be raised to end the conver-
sion period at any time during the transmission. Faster
conversion rates can be obtained by using this tech-
nique if not all the bits are captured before starting a
new cycle. Some system designers use this method by
capturing only the highest order 8 bits and ‘throwing
away’ the lower 2 bits.
B1 B2 B3 B4 B5 B6 B7 B8 B9
t
CSH
t
DATA
t
DATA
Power
Down
**
Power Down
HI-Z
**
NULL
BIT
t
CSH
MCP3001
B9 B8
HI-Z
DS21293C-page 15
B7 B6