CS5530-ISZ Cirrus Logic Inc, CS5530-ISZ Datasheet - Page 13

• Manufacturer Part Number: CS5530-ISZ
• Description: IC ADC 24BIT 1CH W/LNA 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5530-ISZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 6.25 SPs to 3840 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1158 - BOARD EVAL FOR CS5530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1283-5

DS742F3
initialization sequence, the user must also perform
a system reset sequence which is as follows: Write
a logic 1 into the RS bit of the configuration regis-
ter. This will reset the calibration registers and
other logic (but not the serial port). A valid reset
will set the RV bit in the configuration register to a
logic 1. After writing the RS bit to a logic 1, wait
8 master clock cycles, then write the RS bit back to
logic 0. Note that the other bits in the configura-
tion register cannot be written on this write cycle
as they are being held in reset until RS is set back
to logic 0. While this involves writing an entire
word into the configuration register to casue the
RS bit to go to logic 0, the RV bit is a read only bit,
therefore a write to the configuration register will
not overwrite the RV bit. After clearing the RS bit
back to logic 0, read the configuration register to
check the state of the RV bit as this indicates that a
valid reset occurred. Reading the configuration
register clears the RV bit back to logic 0.
Offset Register (1 x 32)
Power Save Select
Reset System
Input Short
Voltage Reference Select
Output Latch
Filter Rate Select
Word Rate
Unipolar/Bipolar
Open Circuit Detect
Offset (1 x 32)
Configuration Register (1 x 32)
Gain Register (1 x 32)
Gain (1 x 32)
Figure 6. CS5530 Register Diagram
Completing the reset cycle initializes the on-chip
registers to the following states:
After the configuration register has been read to
clear the RV bit, the register can then be written to
set the other function bits or other registers can be
written or read.
Once the system initialization or reset is complet-
ed, the on-chip controller is initialized into com-
mand mode where it waits for a valid command
(the first 8-bits written into the serial port are shift-
ed into the command register). Once a valid com-
mand is received and decoded, the byte instructs
the converter to either acquire data from or transfer
data to an internal register, or perform a conversion
or a calibration. The Command Register Descrip-
tions section lists all valid commands.
Configuration Register:
Offset Register:
Gain Register
Register (1 × 8)
Command
Conversion Data
Register (1 x 32)
Data (1 x 32)
00000000(H)
00000000(H)
01000000(H)
Interface
Serial
CS5530
CS
SDI
SDO
SCLK
13