AD7658BSTZ Analog Devices Inc, AD7658BSTZ Datasheet - Page 22

• Manufacturer Part Number: AD7658BSTZ
• Description: IC ADC 12BIT 6CH 250KSPS 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7658BSTZ

• Data Interface: Serial, Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Number Of Converters: 6
• Power Dissipation (max): 143mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Resolution (bits): 12bit
• Sampling Rate: 250kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply Current: 26mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7658CBZ - BOARD EVAL FOR AD7658
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7656/AD7657/AD7658
The V
processor. The voltage on V
the output logic signals.
The V
10 μF decoupling capacitor. These supplies are used for the high
voltage analog input structures on the AD7656/AD7657/AD7658
analog inputs.
DRIVING THE ANALOG INPUTS
Together, the driver amplifier and the analog input circuit used
for the AD7656 must settle for a full-scale step input to a 16-bit
level (0.0015%), which is within the specified 550 ns acquisition
time of the AD7656. The noise generated by the driver amplifier
needs to be kept as low as possible to preserve the SNR and
transition noise performance of the AD7656.
The driver also needs to have a THD performance suitable to
that of the AD7656. The
The
10 pF. If a dual version of the
can be used. The
drive the AD7656/AD7657/AD7658.
INTERFACE SECTION
The AD7656/AD7657/AD7658 provide two interface options, a
parallel interface and a high speed serial interface. The required
interface mode is selected via the SER/ PAR pin. The parallel
interface can operate in word ( W /B = 0) or byte ( W /B = 1) mode.
The interface modes are discussed in the following sections.
AD8021
DRIVE
DD
and V
supply is connected to the same supply as the
needs an external compensation capacitor of
SS
signals should be decoupled with a minimum
AD8610
+9.5V TO +16.5V
–9.5V TO –16.5V
AD8021
and the
DRIVE
SUPPLY
2.5V
REF
AD8021
SUPPLY
ANALOG SUPPLY
controls the voltage value of
meets all these requirements.
VOLTAGE 5V
AD797
SIX ANALOG
10µF
10µF
10µF
10µF
is required, the
INPUTS
+
+
+
+
can also be used to
1
1
DECOUPLING SHOWN ON THE AV
100nF
100nF
100nF
100nF
10µF
+
Figure 26. Typical Connection Diagram
V
AGND
REFCAPA, B, C
AGND
REFIN/OUT
AGND
V
AGND
AD8022
DD
SS
AGND
100nF
AD7656/AD7657/AD7658
AV
Rev. A | Page 22 of 32
CC
DV
CC
100nF
DGND
CC
DV
PIN APPLIES TO EACH AV
Parallel Interface (SER/ PAR = 0)
The AD7656/AD7657/AD7658 consist of six 16-/14-/12-bit
ADCs, respectively. A simultaneous sample of all six ADCs can
be performed by connecting all three CONVST pins together,
CONVST A, CONVST B, and CONVST C. The AD7656/AD7657/
AD7658 need to see a CONVST pulse to initiate a conversion;
this should consist of a falling CONVST edge followed by a
rising CONVST edge. The rising edge of CONVSTx initiates
simultaneous conversions on the selected ADCs. The AD7656/
AD7657/AD7658 contain an on-chip oscillator that is used to
perform the conversions. The conversion time, t
The BUSY signal goes low to indicate the end of conversion.
The falling edge of the BUSY signal is used to place the track-
and-hold into track mode. The AD7656/AD7657/AD7658 also
allow the six ADCs to be converted simultaneously in pairs by
pulsing the three CONVST pins independently. CONVST A is
used to initiate simultaneous conversions on V1 and V2,
CONVST B is used to initiate simultaneous conversions on V3
and V4, and CONVST C is used to initiate simultaneous
conversions on V5 and V6. The conversion results from the
simultaneously sampled ADCs are stored in the output data
registers.
Data can be read from the AD7656/AD7657/AD7658 via the
parallel data bus with standard CS and RD signals ( W /B = 0).
To read the data over the parallel bus, SER/ PAR should be tied
low. The CS and RD input signals are internally gated to enable
the conversion result onto the data bus. The data lines DB0 to
DB15 leave their high impedance state when both CS and RD
are logic low.
CC
+
10µF
CONVST A, B, C
V
DRIVE
D0 TO D15
SER/PAR
100nF
RANGE
RESET
DGND
BUSY
STBY
W/B
H/S
RD
CS
+
DIGITAL SUPPLY
VOLTAGE +3V OR +5V
10µF
INTERFACE
PARALLEL
CC
PIN.
V
DRIVE
µP/µC/DSP
CONV
, is 3 μs.