CS5509-ASZ Cirrus Logic Inc, CS5509-ASZ Datasheet - Page 7

• Manufacturer Part Number: CS5509-ASZ
• Description: IC ADC 16BIT SGNL SUPP 16-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5509-ASZ

• Number Of Converters: 1
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Number Of Bits: 16
• Sampling Rate (per Second): 200
• Data Interface: Serial
• Power Dissipation (max): 2.25mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 20 SPs
• Resolution: 16 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: 1.2 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Maximum Power Dissipation: 2.25 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1100-5

5V SWITCHING CHARACTERISTICS
0V, Logic 1 = VD+; C
Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
3.3V SWITCHING CHARACTERISTICS
Levels: Logic 0 = 0V, Logic 1 = VD+; C
DS125F3
Serial Clock
Serial Clock
Access Time
Maximum Delay Time
Output Float Delay
Serial Clock
Serial Clock
Access Time
Maximum Delay Time
Output Float Delay
SCLK falling to new SDATA bit
SCLK falling to new SDATA bit
17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial
18. If CS is returned high before all data bits are output, the SDATA output will complete the current data
for 2 clock cycles. The propagation delay time may be as great as 2 f
proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than
2 f
port shifting mechanism before falling edges can be recognized.
bit and then go to high impedance.
clk
+ 200 ns after CS goes low.
L
= 50 pF) (Note 2)
Parameter
Parameter
CS High to output Hi-Z (Note 18)
CS High to output Hi-Z (Note 18)
CS Low to data valid (Note 16)
CS Low to data valid (Note 16)
L
= 50 pF) (Note 2)
SCLK falling to Hi-Z
SCLK falling to Hi-Z
Pulse Width High
Pulse Width High
Pulse Width Low
Pulse Width Low
(Note 17)
(Note 17)
(T
A
(T
= 25 °C; VA+, VD+ = 5V ±5%; Input Levels: Logic 0 =
A
= 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input
Symbol
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
sclk
sclk
t
csd
t
csd
fd1
fd2
fd1
fd2
ph
dd
ph
dd
pl
pl
Min
Min
200
200
200
200
0
0
-
-
-
-
-
-
-
-
clk
cycles plus 200 ns. To guarantee
Typ
150
160
Typ
100
400
320
60
60
70
-
-
-
-
-
-
Max
Max
1.25
200
310
150
300
200
600
150
500
2.5
-
-
-
-
CS5509
Unit
MHz
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7