AD9245BCPZ-80 Analog Devices Inc, AD9245BCPZ-80 Datasheet

IC ADC 14BIT 80MSPS 3V 32-LFCSP

AD9245BCPZ-80

Manufacturer Part Number
AD9245BCPZ-80
Description
IC ADC 14BIT 80MSPS 3V 32-LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9245BCPZ-80

Data Interface
Parallel
Number Of Bits
14
Sampling Rate (per Second)
80M
Number Of Converters
3
Power Dissipation (max)
414mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Resolution (bits)
14bit
Sampling Rate
80MSPS
Input Channel Type
Differential, Single Ended
Supply Voltage Range - Analog
2.7V To 3.6V
Supply Current
122mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9245BCP-80EBZ - BOARD EVAL FOR AD9245BCP-80AD9245BCP-40EBZ - BOARD EVAL FOR AD9245BCP-40AD9245BCP-20EBZ - BOARD EVAL FOR AD9245BCP-20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9245BCPZ-80
Manufacturer:
AD
Quantity:
197
Part Number:
AD9245BCPZ-80
Manufacturer:
ADI
Quantity:
1
Part Number:
AD9245BCPZ-80
Manufacturer:
ADI/亚德诺
Quantity:
20 000
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SENSE
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
2. The patented SHA input maintains excellent performance for
3. The AD9245 is pin-compatible with the AD9215, AD9235,
4. The clock DCS maintains overall ADC performance over a
5. The OTR output bit indicates when the signal is beyond the
REFB
VREF
REFT
VIN+
VIN–
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
wide range of clock pulse widths.
selected input range.
SELECT
SHA
REF
FUNCTIONAL BLOCK DIAGRAM
AGND
A/D
AVDD
0.5V
MDAC1
© 2006 Analog Devices, Inc. All rights reserved.
4
CORRECTION LOGIC
DUTY CYCLE
Figure 1.
STABILIZER
OUTPUT BUFFERS
3 V A/D Converte
CLOCK
CLK
AD9245
1 1/2-BIT PIPELINE
8-STAGE
14
PDWN
16
SELECT
MODE DGND
MODE
AD9245
www.analog.com
DRVDD
A/D
3
OTR
D13 (MSB)
D0 (LSB)
r

Related parts for AD9245BCPZ-80

AD9245BCPZ-80 Summary of contents

Page 1

FEATURES Single 3 V supply operation (2 3.6 V) SNR = 72.7 dBc to Nyquist SFDR = 83.0 dBc to Nyquist Low power 366 MSPS 300 MSPS 165 MSPS ...

Page 2

AD9245 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 7 Switching ...

Page 3

SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate p-p differential input, 1.0 V internal reference, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error 1 Gain Error ...

Page 4

AD9245 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS p-p differential input, 1.0 V external reference, unless otherwise noted. Table 2. Parameter RESOLUTION ACCURACY No Missing Codes 1 Offset Error Gain Error 1 ...

Page 5

AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 3. Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 ...

Page 6

AD9245 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 4. Parameter SIGNAL-TO-NOISE RATIO (SNR ...

Page 7

DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted. Table 5. Parameter LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current ...

Page 8

AD9245 SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted. Table 6. Parameter Min CLOCK INPUT PARAMETERS Maximum Conversion Rate 20 Minimum Conversion Rate CLK Period 50.0 1 CLK Pulse Width High 15.0 1 CLK Pulse ...

Page 9

ABSOLUTE MAXIMUM RATINGS Table 7. Parameter With Respect to Min ELECTRICAL AVDD AGND –0.3 DRVDD DGND –0.3 AGND DGND –0.3 AVDD DRVDD –3 D13 DGND –0.3 CLK, MODE AGND –0.3 VIN+, VIN– AGND –0.3 VREF AGND –0.3 SENSE ...

Page 10

AD9245 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay ( The delay between the ...

Page 11

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 9. Pin Function Descriptions Pin No. Mnemonic 1, 3 DNC 2 CLK 4 PDWN (LSB) to D13 (MSB) 15 DGND 16 DRVDD 21 OTR 22 MODE 23 ...

Page 12

AD9245 EQUIVALENT CIRCUITS AVDD VIN+, VIN– Figure 4. Equivalent Analog Input Circuit AVDD MODE Figure 5. Equivalent MODE Input Circuit 20kΩ Rev Page DRVDD D13-D0, OTR Figure 6. Equivalent Digital Output Circuit AVDD CLK, PDWN ...

Page 13

TYPICAL PERFORMANCE CHARACTERISTICS DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, T AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted. 0 –10 –20 –30 –40 –50 –60 –70 ...

Page 14

AD9245 0 AIN = –6.5dBFS –10 SNR = 73.4dBFS SFDR = 86.0dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 ...

Page 15

INPUT FREQUENCY (MHz) Figure 20. SNR vs. Input Frequency 90 SFDR (DCS ON SFDR (DCS OFF ...

Page 16

AD9245 0 AIN = –0.5dBFS SNR = 72.7dBc –20 ENOB = 11.7 BITS SFDR = 81.3dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz 2.0 1.5 1.0 ...

Page 17

CODE Figure 32. AD9245-20 Typical INL 0 AIN = –0.5dBFS SNR = 73.4dBc –20 ENOB = 11.9 BITS SFDR = 95.0dBc –40 ...

Page 18

AD9245 THEORY OF OPERATION The AD9245 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections consisting of a 4-bit first stage followed by eight 1.5-bit ...

Page 19

The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as VREF = VCM MIN ...

Page 20

AD9245 JITTER CONSIDERATIONS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t INPUT calculated with the following equation: ...

Page 21

As detailed in Table 11, the data format can be selected for either offset binary or twos complement. TIMING The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay ...

Page 22

AD9245 VIN+ VIN– VREF + 10μF 0.1μF SELECT R2 LOGIC SENSE R1 0.5V AD9245 Figure 47. Programmable Reference Configuration EXTERNAL REFERENCE OPERATION The use of an external reference can be necessary to enhance the gain accuracy of the ADC or ...

Page 23

P2 5.0V VAMP VDL 2.5V GND 2.5V DRVDD GND AVDD 3.0V D10 17 D11 18 D12 19 D13 20 OTR 21 MODE 22 SENSE 23 VREF 24 Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT Rev Page ...

Page 24

AD9245 Figure 50. LFCSP Evaluation Board Schematic—Digital Path Rev Page ...

Page 25

Figure 51. LFCSP Evaluation Board Schematic—Clock Input Rev Page AD9245 ...

Page 26

AD9245 Figure 52. LFCSP Evaluation Board Layout, Primary Side Figure 53. LFCSP Evaluation Board Layout, Secondary Side Figure 54. LFCSP Evaluation Board Layout, Ground Plane Figure 55. LFCSP Evaluation Board Layout, Power Plane Rev Page ...

Page 27

Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev Page AD9245 ...

Page 28

AD9245 Table 12. LFCSP Evaluation Board Bill of Materials 1 Item Qty. Omit Reference Designator 1 18 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C17, C18, C27, ...

Page 29

... SEATING PLANE ORDERING GUIDE Model Temperature Range AD9245BCP-80 –40°C to +85°C AD9245BCPRL7–80 –40°C to +85°C 2 AD9245BCPZ-80 –40°C to +85°C AD9245BCPZRL7-80 2 –40°C to +85°C 2 AD9245BCPZ-65 –40°C to +85°C 2 AD9245BCPZRL7-65 –40°C to +85°C 2 AD9245BCPZ-40 – ...

Page 30

AD9245 NOTES Rev Page ...

Page 31

NOTES Rev Page AD9245 ...

Page 32

AD9245 NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03583–0–1/06(D) Rev Page ...

Related keywords