MAX11603EEE+ Maxim Integrated Products, MAX11603EEE+ Datasheet - Page 8

• Manufacturer Part Number: MAX11603EEE+
• Description: IC ADC SERIAL 8BIT 8CH 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX11603EEE+

• Number Of Bits: 8
• Sampling Rate (per Second): 188k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 1.75mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Resolution: 8 bit
• Interface Type: I2C
• Snr: 49 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 666.7 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
The MAX11600–MAX11605 ADCs use successive-
approximation conversion techniques and input T/H cir-
cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX11600/MAX11601
are 4-channel ADCs, the MAX11602/MAX11603 are
8-channel ADCs and the MAX11604/MAX11605 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional dia-
gram for the MAX11604/MAX11605.
The MAX11600–MAX11605 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX11601/MAX11603/MAX11605 feature a 2.048V
internal reference and the MAX11600/MAX11602/
MAX11604 feature a 4.096V internal reference. All
devices can be configured for use with an external refer-
ence from 1V to V
The MAX11600–MAX11605 analog input architecture
contains an analog input multiplexer (MUX), a T/H
capacitor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer con-
nects C
the Configuration/Setup Bytes (Write Cycle) section). The
8
MAX11600
MAX11601
1, 2, 3
_______________________________________________________________________________________
—
—
—
—
—
4
5
6
7
8
T/H
to the analog input selected by CS[3:0] (see
MAX11602
MAX11603
12, 11, 10
2, 3, 4
PIN
9–5
DD
13
14
15
16
—
—
—
1
Analog Input and Track/Hold
.
Detailed Description
MAX11604
MAX11605
12, 11, 10
4, 3, 2
9–5
—
—
13
14
15
16
—
1
Power Supply
AIN 0, AIN 1, AIN 2
AIN8–AIN10
AIN3–AIN7
AIN11/REF
AIN3/REF
NAME
GND
SDA
N.C.
REF
SCL
V
DD
Analog Inputs
Analog Input 3/Reference Input/Output. Selected in the setup register
(see Tables 1 and 6).
Reference Input/Output. Selected in the setup register (see Tables 1
and 6).
Analog Input 11/Reference Input/Output. Selected in the setup
register (see Tables 1 and 6).
Clock Input
Data Input/Output
Ground
Positive Supply. Bypass to GND with a 0.1µF capacitor.
No Connection
charge on C
pseudo-differential mode, the analog input multiplexer
connects C
CS[3:0]. The charge on C
tive analog input when converted.
The MAX11600–MAX11605 input configuration is
pseudo-differential in that only the signal at the positive
analog input is sampled with the T/H circuitry. The nega-
tive analog input signal must remain stable within
±0.5 LSB (±0.1 LSB for best results) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from the negative analog input to GND.
See the Single-Ended/Pseudo-Differential Input section.
During the acquisition interval, the T/H switches are in
the track position and C
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva-
lent to transferring a charge of 18pF
from C
ing a digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
T/H
T/H
as a sample of the input signal.
to the binary weighted capacitive DAC, form-
T/H
T/H
to the positive analog input selected by
is referenced to GND when converted. In
FUNCTION
T/H
T/H
charges to the analog input
is referenced to the nega-
Pin Description

(V
IN
+ - V
IN
-)