MAX1113CEE+ Maxim Integrated Products, MAX1113CEE+ Datasheet - Page 8

• Manufacturer Part Number: MAX1113CEE+
• Description: IC ADC 8-BIT 50KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1113CEE+

• Number Of Bits: 8
• Sampling Rate (per Second): 50k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 680µW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 4
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Differential
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE)
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Power Dissipation: 667 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
The MAX1112/MAX1113 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
The sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1112
channels with Table 1 and the MAX1113 channels with
Table 2.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND if necessary.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
Figure 3. Typical Operating Circuit
8
_______________Detailed Description
ANALOG
INPUTS
_______________________________________________________________________________________
1 F
CH7
CH0
REFOUT
REFIN
MAX1112
MAX1113
SSTRB
DGND
AGND
DOUT
SHDN
SCLK
COM
DIN
V
CS
DD
Pseudo-Differential Input
0.1 F
1 F
+5V
SCK (SK)
MOSI (SO)
MISO (SI)
V
I/O
DD
CPU
V
HOLD
SS
. The
acquisition interval spans two SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 8-bit resolution. This
action is equivalent to transferring a charge of 18pF x
(V
itive DAC, which in turn forms a digital representation of
the analog input signal.
The T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
positive input connects back to IN+, and C
charges to the input signal.
Figure 4. Equivalent Input Circuit
IN+
*MAX1112 ONLY
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
HOLD
CH6*
CH4*
CH5*
CH7*
COM
CH0
CH1
CH2
CH3
- V
REFIN
IN-
as a sample of the signal at IN+.
) from C
INPUT
MUX
HOLD
C
CAPACITIVE DAC
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
SWITCH
–
HOLD
C
18pF
from the positive input (IN+) to the
HOLD
TRACK
SWITCH
+
to the binary-weighted capac-
T/H
6.5k
R
IN
HOLD
ZERO
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
Track/Hold
HOLD