MAX1247BCEE+ Maxim Integrated Products, MAX1247BCEE+ Datasheet - Page 11

• Manufacturer Part Number: MAX1247BCEE+
• Description: IC ADC SRL 4CH 12BIT 2.7V 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1247BCEE+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 667mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: External
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
where R
input signal, and t
that source impedances below 1kΩ do not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Table 1. Control-Byte Format
ACQ
BIT 7
(MSB)
START
BIT
7(MSB)
6
5
4
3
2
1
0(LSB)
, is the maximum time the device takes to acquire
IN
= 9kΩ, R
t
NAME
ACQ
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT 6
SEL2
______________________________________________________________________________________
= 9 x (R
ACQ
S
= the source impedance of the
is never less than 1.5µs. Note
S
+ R
DESCRIPTION
The first logic “1” bit after CS goes low defines the beginning of the control byte.
These three bits select which of the four channels are used for the conversion (Tables 2 and 3).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
Selects clock and power-down modes.
PD1
0
0
1
1
BIT 5
SEL1
IN
Input Bandwidth
) x 16pF
PD0
0
1
0
1
Serial 12-Bit ADCs in QSOP-16
+2.7V, Low-Power, 4-Channel,
BIT 4
SEL0
Mode
Full power-down
Fast power-down
Internal clock mode
External clock mode
Internal protection diodes, which clamp the analog input
to V
from AGND - 0.3V to V
However, for accurate conversions near full scale, the
inputs must not exceed V
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 4mA.
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1246/MAX1247’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX1246/MAX1247 are compatible with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time. Using the Typical Operating
BIT 3
UNI/BIP
DD
and AGND, allow the channel input pins to swing
BIT 2
SGL/DIF
How to Start a Conversion
Analog Input Protection
DD
DD
+ 0.3V without damage.
by more than 50mV or be
BIT 1
PD1
BIT 0
(LSB)
PD0
11