MAX1081BEUP+ Maxim Integrated Products, MAX1081BEUP+ Datasheet - Page 10

• Manufacturer Part Number: MAX1081BEUP+
• Description: IC ADC 10BIT 300KSPS 20-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1081BEUP+

• Number Of Bits: 10
• Sampling Rate (per Second): 300k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 8.0mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 10 bit
• Input Type: Differential
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 559 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Figure 1. Load Circuits for Enable Time
10
DOUT
PIN
1–8
10
11
12
13
14
15
16
17
18
19
20
______________________________________________________________________________________
9
a) High-Z to V
6k
CH0–CH7
REFADJ
OH
SSTRB
NAME
SHDN
DOUT
SCLK
COM
V
V
GND
GND
REF
DIN
and V
CS
DD2
DD1
OL
to V
OH
C
Sampling Analog Inputs
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA
(typ).
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a 2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
V
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
V
Analog and Digital Ground
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
Serial Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)
Positive Supply Voltage
Positive Supply Voltage
20pF
LOAD
DD1
DD1
.
.
b) High-Z to V
DOUT
V
DD2
OL
and V
6k
C
GND
20pF
LOAD
OH
to V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
DOUT
6k
a) V
OH
GND
to High-Z
C
20pF
LOAD
Pin Description
DOUT
b) V
OL
V
to High-Z
DD2
6k
C
GND
20pF
LOAD