MAX1231BEEG+ Maxim Integrated Products, MAX1231BEEG+ Datasheet - Page 19

• Manufacturer Part Number: MAX1231BEEG+
• Description: IC ADC 12BIT 300KSPS 24-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1231BEEG+

• Number Of Bits: 12
• Sampling Rate (per Second): 300k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 762mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Number Of Adc Inputs: 16
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 12 bit
• Input Type: Differential
• Interface Type: 3-Wire (SPI, QSPI, MICROWIRE)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 3.3 V
• Maximum Power Dissipation: 762 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100µs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, or if an external ref-
erence is selected but a temperature measurement is
being requested, wait 65µs with CS high after writing
the conversion byte to extend the acquisition and allow
the internal reference to power up. To perform a tem-
perature measurement, write 24 bytes (192 cycles) of
zeros after the conversion byte. The temperature result
appears on DOUT during the last 2 bytes of the 192
cycles.
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
Figure 7. Clock Mode 11
DIN
SCLK
DOUT
EOC
CS
Conversions Using the Serial Interface
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Externally Clocked Acquisitions and
Performing Conversions in Clock Mode 11
Partial Reads and Partial Writes
______________________________________________________________________________________
(ACQUISITION1)
Temp Sensor, Internal Reference
(CONVERSION BYTE)
12-Bit 300ksps ADCs with FIFO,
MSB1
(CONVERSION1)
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = V
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
For best performance, use PC boards. Do not use wire-
wrap boards. Board layout should ensure that digital
and analog signal lines are separated from each other.
Do not run analog and digital (especially clock) signals
parallel to one another or run digital lines underneath the
MAX1227/MAX1229/MAX1231 package. High-frequen-
cy noise in the V
mance. Bypass the V
to GND, close to the V
lengths for best supply-noise rejection. If the power sup-
ply is very noisy, connect a 10Ω resistor in series with
the supply to improve power-supply filtering. For the
TQFN package, connect its exposed pad to ground.
Layout, Grounding, and Bypassing
DD
(ACQUISITION2)
DD
power supply can affect perfor-
LSB1
DD
supply with a 0.1µF capacitor
pin. Minimize capacitor lead
Transfer Function
REF
MSB2
/ 2.5V for
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