CS5511-ASZ Cirrus Logic Inc, CS5511-ASZ Datasheet - Page 18

• Manufacturer Part Number: CS5511-ASZ
• Description: IC ADC 16BIT INTERNAL OSC 8SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5511-ASZ

• Number Of Converters: 1
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Number Of Bits: 16
• Sampling Rate (per Second): 326
• Data Interface: Serial
• Power Dissipation (max): 2mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 16 SPs to 326 SPs
• Resolution: 16 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: 250 mV to 5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1705

cessively overranged. If the OD bit is set, the con-
version data bits can be completely erroneous. The
OD flag bit will be cleared to logic 0 four output
words after the modulator becomes stable again.
The OD flag can occur independent of OF with a
spike on the input. Both flag bits should be tested
if any overrange condition occurs.
Table 3 illustrates the output coding for the
CS5510/11/12/13. Conversions are output as
two's complement values representing bipolar in-
put signals.
2.5.4
The CS5510/11/12/13 have a modified Sinc
tal filter that provides CLK/612 Hz conversion rates
18
D23
D23
D11
D11
11
11
0
0
Note: VFS in the table equals the voltage between AIN+ and AIN-. See text about error flags
Digital Filter
Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits).
Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits).
Bipolar Input Voltage
D10
D10
D22
D22
OF
OF
10
10
>(VFS-1.5 LSB)
under overrange conditions.
-VFS+0.5 LSB
VFS-1.5 LSB
-0.5 LSB
D21
D21
OD
OD
D9
D9
9
9
D20
D20
D8
D8
0
8
0
8
Table 3. CS5510/11/12/13 Output Coding.
Two's Complement (20-Bit)
MSB
D19
D19
D7
D7
7
0
7
D18
D18
D6
D6
18
4
6
0
6
7FFFF
7FFFF
7FFFE
FFFFF
00000
80001
80000
digi-
-----
-----
-----
D17
D17
D5
D5
17
5
0
5
(CLK represents SCLK for the CS5510/12 and the
internal oscillator for the CS5511/13). The filters
are optimized to yield better than 80 dB rejection
between 47 Hz to 63 Hz (i.e. 80 dB minimum rejec-
tion for both 50 Hz and 60 Hz) when the master
clock is 32.768 kHz. The filter has a response as
shown in Figure 20. Table 4 shows the filter re-
sponse for frequencies from 38 Hz to 71 Hz. Note
that the response of the CS5511/13 will be similar,
but the frequencies scale with the on-chip oscilla-
tor’s frequency, which can be from 32 kHz to
96 kHz (i.e. conversion rates can vary between
53 Sps to 159 Sps). Further note that after initial
power up, or after returning from sleep mode, the
filter requires four conversion cycles to produce a
D16
D16
D4
D4
16
4
0
4
Two's Complement (16-Bit)
MSB
D15
D15
D3
D3
15
3
3
7FFF
7FFF
7FFE
FFFF
0000
8001
8000
-----
-----
-----
D14
D14
D2
D2
14
14
2
2
CS5510/11/12/13
D13
D13
D1
D1
13
13
1
1
D12
LSB
D12
LSB
D0
D0
DS337F4
12
12