AD9042ASTZ Analog Devices Inc, AD9042ASTZ Datasheet - Page 17

• Manufacturer Part Number: AD9042ASTZ
• Description: IC ADC 12BIT 41MSPS 44-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9042ASTZ

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 41M
• Number Of Converters: 3
• Power Dissipation (max): 735mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Resolution (bits): 12bit
• Sampling Rate: 41MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 5V
• Supply Voltage Range - Digital: 5V
• Supply Current: 119mA
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: Pipelined
• Sample Rate: 41MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 1.9/2.9V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 735mW
• Differential Linearity Error: ±1LSB
• Integral Nonlinearity Error: ±0.75LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 38 shows the block diagram of a typical channelizer.
Channelizers consist of a complex NCO (numerically controlled
oscillator), dual multiplier (mixer), and matched digital filters.
These are the same functions that would be required in an
analog receiver but implemented in digital form. The digital
output from the channelizer is the desired carrier, frequently in
I and Q format; all other signals are filtered and removed based
on the filtering characteristics desired. Because the channelizer
output consists of one selected RF channel, one tuner chip is
required for each frequency received, although only one
wideband RF receiver is needed for the entire band. Data from
the channelizer can then be processed using a digital signal
processor such as the ADSP-2181 or the SHARC ADSP-21062
processor. This data may then be processed through software to
demodulate the information from the carrier.
Figure 39 shows a typical wideband receiver subsystem based
around the AD9042. This strip consists of a wideband IF filter,
amplifier, ADC, latches, channelizer, and interface to a digital
signal processor. This design shows a typical clocking scheme
used in many receiver designs. All timing within the system is
referenced back to a single clock. Although this is not necessary,
it facilitates PLL design, ease of manufacturing, system test, and
calibration. Keeping in mind that the overall performance goal
is to maintain the best possible dynamic range, many choices
must be considered.
One of the biggest challenges is selecting the amplifier used to
drive the AD9042. Because this is a communications application,
the key specification for this amplifier is spurious-free dynamic
range (SFDR). An amplifier should be selected that can provide
SFDR performance better than 80 dB into 250 Ω. One such
amplifier is the AD9631. These low spurious levels are necessary
because harmonics due to the drive amplifier and ADC can
distort the desired signals of interest.
Two other key considerations for the digital wideband receiver
are converter sample rate and IF frequency range. Because
performance of the AD9042 converter is nearly independent
of both sample rate and analog input frequency (see Figure 6,
Figure 7, and Figure 10), the designer has greater flexibility in the
selection of these parameters. Also, because the AD9042 is a
PRESELECT
FILTER
LNA
DRIVE
864MHz
SYNTHESIZER
LO
40.96MHz
REFERENCE
M/N PLL
CLOCK
5MHz TO 15MHz
PASS BAND
REF
IN
Figure 39. Simplified 5 MHz Wideband “A” Carrier Receiver
5V (A)
AIN
ENCODE
ENCODE
AD9042
Rev. B | Page 17 of 24
D11
D0
5V (D)
499Ω
bipolar device, power dissipation is not a function of sample
rate. Thus, there is no penalty paid in power by operating at
faster sample rates. By carefully selecting input frequency range
and sample rate, the drive amplifier and ADC harmonics can
actually be placed out-of-band. Thus, other components such as
filters and IF amplifiers may actually end up being the limiting
factor on dynamic range.
For example, if the system has second and third harmonics that
are unacceptably high, the careful selection of the encode rate
and signal bandwidth can place these second and third harmonics
out-of-band. For the case of an encode rate equal to 40.96 MSPS
and a signal bandwidth of 5.12 MHz, placing the fundamental
at 5.12 MHz places the second and third harmonics out-of-
band as shown in Table 7.
Table 7. Example Frequency Plan
Parameter
Encode Rate
Fundamental
Second Harmonic
Third Harmonic
Another option is found through band-pass sampling. If the
analog input signal range is from dc to FS/2, then the amplifier
and filter combination must perform to the specification required.
However, if the signal is placed in the third Nyquist zone (FS to
3 FS/2), the amplifier is no longer required to meet the harmonic
performance required by the system specifications because all
harmonics fall outside the pass-band filter. For example, the
pass-band filter ranges from f
would span from 2 FS to 3 FS, well outside the range of the
pass-band filter. The burden then is placed on the filter design,
provided that the ADC meets the basic specifications at the
frequency of interest. In many applications, this is a worthwhile
trade-off because many complex filters can easily be realized
using SAW and LCR techniques alike at these relatively high IF
frequencies. Although the harmonic performance of the drive
amplifier is relaxed by this technique, intermodulation
performance cannot be sacrificed because intermods must be
assumed to fall in-band for both amplifiers and converters.
BUFFER
CMOS
12
CHANNELIZER
CLK
I AND Q
DATA
ADSP-2181
Value
40.96 MSPS
5.12 MHz to 10.24 MHz
10.24 MHz to 20.48 MHz
15.36 MHz to 10.24 MHz
S
to 3 FS/2. The second harmonic
NETWORK
CONTROLLER
INTERFACE
AD9042