AD9430BSVZ-170 Analog Devices Inc, AD9430BSVZ-170 Datasheet

IC ADC 12BIT 170MSPS 3.3V100TQFP

AD9430BSVZ-170

Manufacturer Part Number
AD9430BSVZ-170
Description
IC ADC 12BIT 170MSPS 3.3V100TQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9430BSVZ-170

Data Interface
Parallel
Number Of Bits
12
Sampling Rate (per Second)
170M
Number Of Converters
1
Power Dissipation (max)
1.43mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad
Resolution (bits)
12bit
Sampling Rate
170MSPS
Input Channel Type
Differential, Single Ended
Supply Voltage Range - Digital
3V To 3.6V
Supply Current
335mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FEATURES
SNR = 65 dB @ f
ENOB of 10.6 @ f
SFDR = 80 dBc @ f
Excellent linearity:
2 output data options:
LVDS at 210 MSPS
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.3 W typical @ 210 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Data sync input and data clock output provided
Clock duty cycle stabilizer
GENERAL DESCRIPTION
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The product operates up to a 210 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a track-and-hold (T/H) and
reference, are included on the chip to provide a complete
conversion solution.
The ADC requires a 3.3 V power supply and a differential
ENCODE clock for full performance operation. The digital
outputs are TTL/CMOS or LVDS compatible and support either
twos complement or offset binary format. Separate output
power supply pins support interfacing with 3.3 V CMOS logic.
Two output buses support demultiplexed data up to 105 MSPS
rates in CMOS mode. A data sync input is supported for proper
output data port alignment in CMOS mode, and a data clock
output is available for proper output data timing. In LVDS
mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100-lead, surface-mount plastic package
(100 e-PAD TQFP) specified over the industrial temperature
range (–40°C to +85°C).
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DNL = ±0.3 LSB (typical)
INL = ±0.5 LSB (typical)
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS
Interleaved or parallel data output option
IN
IN
= 70 MHz @ 210 MSPS
IN
= 70 MHz @ 210 MSPS (–0.5 dBFS)
= 70 MHz @ 210 MSPS (–0.5 dBFS)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
.
CLK+
CLK–
VIN+
VIN–
DS+
DS–
High performance.
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
Low power.
Consumes only 1.3 W @ 210 MSPS.
Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 3.3 V supply simplifies system power supply
design.
Out of range (OR) feature.
The OR output bit indicates when the input signal is
beyond the selected input range.
Pin compatible with 10-bit AD9411 (LVDS only).
AD9430
MANAGEMENT
S1
AND-HOLD
TRACK-
CLOCK
FUNCTIONAL BLOCK DIAGRAM
SENSE
S2
REFERENCE
SCALABLE
12-Bit, 170/210 MSPS
©2005–2010 Analog Devices, Inc. All rights reserved.
3.3 V A/D Converter
VREF
PIPELINE
12-BIT
CORE
ADC
S4
Figure 1.
AGND DRGND DRVDD AVDD
SELECT CMOS
12
S5
OR LVDS
OUTPUTS
OUTPUTS
CMOS
LVDS
AD9430
www.analog.com
DCO+
DCO–
DATA,
OVERRANGE
IN LVDS OR
2-PORT CMOS

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AD9430BSVZ-170 Summary of contents

Page 1

FEATURES SNR = MHz @ 210 MSPS IN ENOB of 10 MHz @ 210 MSPS (–0.5 dBFS) IN SFDR = 80 dBc @ MHz @ 210 MSPS ...

Page 2

AD9430 TABLE OF CONTENTS DC Specifications ............................................................................. 4 AC Specifications.............................................................................. 6 Digital Specifications........................................................................ 7 Switching Specifications .................................................................. 8 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 10 Explanation of Test Levels ......................................................... 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... ...

Page 3

REVISION HISTORY 9/10—Rev Rev. E Change to General Description Section.........................................1 Change to Operating Temperature Range Parameter, Table 5..10 Change to Figure 4 ..........................................................................11 Change to Figure 5 ..........................................................................13 Added Exposed Pad Notation to Outline Dimensions ..............42 8/05—Rev. C ...

Page 4

AD9430 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3 –40°C, T MIN unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset ...

Page 5

Parameter POWER SUPPLY (CMOS Mode) AVDD DRVDD Supply Currents 5 I (AVDD = 3.3 V) AVDD 5 I (DRVDD = 3.3 V) DRVDD 5 Power Dissipation Power Supply Rejection 1 Internal reference mode; SENSE = Floats. 2 External reference mode; ...

Page 6

AD9430 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3 –40°C, T MIN 1 unless otherwise noted. Table 2. Parameter SNR Analog Input @ –0.5 dBFS SINAD Analog Input @ –0.5 dBFS EFFECTIVE NUMBER OF BITS (ENOB) ...

Page 7

DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3 –40°C, T MIN Table 3. Parameter Temp ENCODE AND DS INPUTS 1 (CLK+, CLK–, DS+, DS–) 2 Differential Input Voltage Full 3 Common-Mode Voltage Full Input Resistance Full ...

Page 8

AD9430 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3 –40°C, T MIN Table 4. Parameter (Conditions) 1 Maximum Conversion Rate 1 Minimum Conversion Rate 1 CLK+ Pulse Width High ( CLK+ Pulse Width ...

Page 9

TIMING DIAGRAMS CLK+ CLK– DS+ DS– t HDS INTERLEAVED DATA OUT PORT A STATIC DA11–DA0 PORT B STATIC DB11–DB0 PARALLEL DATA OUT PORT A STATIC DA11–DA0 PORT B STATIC DB11–DB0 DCO– STATIC DCO+ N– ...

Page 10

AD9430 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD, DRVDD 4 V Analog Inputs −0 AVDD + 0.5 V Digital Inputs −0 DRVDD + 0.5 V REFIN Inputs –0 AVDD + 0.5 V Digital ...

Page 11

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 PIN 1 2 DNC S4 3 AGND DNC 7 AVDD 8 AGND 9 SENSE 10 VREF 11 AGND 12 13 AGND AVDD 14 AVDD 15 AGND ...

Page 12

AD9430 Pin Number 47, 54, 62, 75, 83 48, 53, 61, 67, 74 ...

Page 13

S5 PIN 1 2 DNC AGND LVDSBIAS 7 AVDD 8 AGND 9 SENSE 10 VREF 11 AGND 12 13 AGND AVDD 14 AVDD 15 AGND 16 AGND 17 AVDD 18 ...

Page 14

AD9430 Pin Number 47, 54, 62, 75, 83 48, 53, 61, 67, 74 ...

Page 15

EQUIVALENT CIRCUITS AVDD 12kΩ CLK+ OR 150Ω 150Ω DS+ 10kΩ Figure 6. ENCODE and DS Input 3.5k Ω 3.5k Ω VIN+ 20k Ω Figure 7. Analog Inputs S1, S2, S4, S5 30k Ω Figure Inputs 12kΩ ...

Page 16

AD9430 TYPICAL PERFORMANCE CHARACTERISTICS Charts at 170 MSPS, 210 MSPS for –170, –210 grades, respectively. AVDD, DRVDD = 3 25°C, A scale = 1.536 V, internal reference unless otherwise noted. 0 SNR = 65.2dB –10 SINAD = ...

Page 17

MHz Figure 18. FFT 210 MSPS MHz @ –0.5 dBFS, LVDS Mode SFDR 75 ...

Page 18

AD9430 –170 SNR –170 SINAD 100 150 200 250 A (MHz) IN Figure 24. SNR and SINAD vs. A Frequency –0.5 dBFS, LVDS ...

Page 19

ANALOG SUPPLY CURRENT CMOS 350 MODE 300 ANALOG SUPPLY 250 CURRENT LVDS OUTPUT SUPPLY MODE CURRENT LVDS 200 MODE 150 100 OUTPUT SUPPLY CURRENT CMOS 50 MODE 0 100 120 140 160 180 ENCODE (MSPS) Figure 30. I and ...

Page 20

AD9430 1.250 1.245 1.240 1.235 1.230 1.225 2.5 2.7 2.9 3.1 3.3 AVDD (V) Figure 36. V Output Voltage vs. AVDD REF 95 THIRD 90 SECOND 85 SFDR –50 –30 – TEMPERATURE (°C) ...

Page 21

SFDR dBc LVDS MODE 60 FULL SCALE = 1 80dB REFERENCE LINE 10 0 –90 –80 –70 –60 –50 –40 –30 Figure 42. SFDR vs. A Input Level 10.3 MHz, 210 ...

Page 22

AD9430 4.5 TCPD (CLOCKOUT RISING) 4.0 3.5 TPDR (DATA RISING) 3.0 2.5 –40 – TEMPERATURE (°C) Figure 48. Propagation Delay vs. Temperature, CMOS Mode, 170 MSPS/210 MSPS 900 800 700 600 500 TPDF (DATA FALLING) 400 300 ...

Page 23

TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...

Page 24

AD9430 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the ...

Page 25

APPLICATION NOTES THEORY OF OPERATION The AD9430 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 12-bit core. For ease ...

Page 26

AD9430 ANALOG INPUT The analog input to the AD9430 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN– should match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs ...

Page 27

LVDS OUTPUTS The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin S2. LVDS outputs are available when S2 = VDD and a 3.74 kΩ RSET resistor is placed at Pin 7 (LVDSBIAS) to ...

Page 28

AD9430 EVALUATION BOARD, CMOS MODE The AD9430 evaluation board offers an easy way to test the AD9430 in CMOS mode. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered ...

Page 29

CMOS DATA OUTPUTS The ADC CMOS digital outputs are latched on the board by four LVT574s; the latch outputs are available at the two 40-pin connectors at Pin 11 through Pin 33 on P23 (Channel A) and Pin 11 through ...

Page 30

AD9430 TROUBLESHOOTING If the board does not seem to be working correctly, try the following: • Verify power at IC pins. • Check that all jumpers are in the correct position for the desired mode of operation. • Verify that ...

Page 31

Table 11 CMOS PCB Evaluation Board Bill of Material No. Quantity Reference Designator 1 47 C1, C3–C11, C15–C44, C47, C48, C58–C62 C12 4 29 C13, C14, C45, C46, C50–C57, C68-C84 5 6 C49, C63–C67 ...

Page 32

AD9430 PTMICA04 PTMICA04 PTMICA04 P4 P21 P22 GND 82 DRVDD GND 86 GND 87 VCC 88 VCC 89 VCC 90 GND 91 GND 92 GND 93 VCC 94 VCC 95 GND ...

Page 33

VCC + C64 C16 C17 C19 C21 10μF 0.1μF 0.1μF 0.1μF 0.1μF GND VCC C68 C69 C70 C71 C72 0.01μF 0.01μF 0.01μF 0.01μF 0.01μF GND VDL + C67 C46 C50 C51 C52 10μF 0.01μF 0.01μF 0.01μF 0.01μF GND DRVDD + ...

Page 34

AD9430 Figure 61. PCB Top-Side Silkscreen Figure 62. PCB Top-Side Copper Figure 63. PCB Ground Layer Figure 64. PCB Split Power Plane Rev Page ...

Page 35

Figure 65. PCB Bottom-Side Copper Figure 66. PCB Bottom-Side Silkscreen Rev Page AD9430 ...

Page 36

AD9430 EVALUATION BOARD, LVDS MODE The AD9430 evaluation board offers an easy way to test the AD9430 in LVDS mode. (The board is also compatible with the AD9411.) It requires a clock source, an analog input signal, and a 3.3 ...

Page 37

Table 13. LVDS PCB Evaluation Board Bill of Material No. Quantity Reference Designator 1 33 C1, C4–C11, C15–C17, C19–C32, C35, C36, C58–C62 C3, C18, C39, C40 2 4 C33, C34, C37, C38 3 4 C63–C66 ...

Page 38

AD9430 GND 82 DRVDD GND GND 87 VCC 88 VCC 89 VCC 90 GND 91 GND 92 GND 93 VCC 94 VCC 95 GND 96 GND 97 VCC 98 VCC ...

Page 39

VCC + C64 C16 C17 C19 C21 10μF 0.1μF 0.1μF 0.1μF 0.1μF GND TO USE VF561 CRYSTAL GND R28 JN00158 100Ω E/D VCC OUTPUTB 2 5 R22 GND GND OUTPUT 3 4 100Ω U9 POWER DOWN USE ...

Page 40

AD9430 F Figure 70. PCB Top-Side Silkscreen—LVDS Figure 71. PCB Top-Side Copper—LVDS Figure 72. PCB Ground Layer—LVDS Figure 73. PCB Split Power Plane—LVDS Rev Page ...

Page 41

Figure 74. PCB Bottom-Side Copper—LVDS Figure 75. PCB Bottom-Side Silkscreen—LVDS Rev Page AD9430 ...

Page 42

... BSC ORDERING GUIDE 1 Model Temperature Range AD9430BSV-170 −40°C to +85°C AD9430BSVZ-170 −40°C to +85°C AD9430BSV-210 −40°C to +85°C AD9430BSVZ-210 −40°C to +85° RoHS Compliant Part. 14.00 BSC PIN 1 TOP VIEW ...

Page 43

NOTES Rev Page AD9430 ...

Page 44

AD9430 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02607-0-9/10(E) Rev Page ...

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