MAX1191ETI+ Maxim Integrated Products, MAX1191ETI+ Datasheet - Page 16

• Manufacturer Part Number: MAX1191ETI+
• Description: IC ADC 8BIT 7.5MSPS DUAL 28-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1191ETI+

• Number Of Bits: 8
• Sampling Rate (per Second): 7.5M
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC
Table 1. Reference Modes
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1191
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
to midsupply (V
The MAX1191 full-scale analog input range is ±V
with a common-mode input range of V
is the difference between V
MAX1191 provides three modes of reference operation.
The voltage at REFIN (V
ation mode (Table 1).
In internal reference mode, connect REFIN to V
leave REFIN unconnected. V
to be 0.512V ±3%. COM, REFP, and REFN are low-
impedance outputs with V
+ V
REFN, and COM each with a 0.33µF capacitor.
In buffered external reference mode, apply a 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with V
V
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for COM, REFP, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
(Figure
reference sources. Drive V
16
DD
REF
/2 + V
______________________________________________________________________________________
/2, and V
4) and can be driven through separate, external
1.024V ±10%
>0.8 x V
V
REFIN
<0.3V
REFIN
DD
REFN
DD
/4, and V
Analog Inputs and Reference
/2) for optimum performance.
= V
REFIN
COM
DD
REFN
COM
/2 - V
REF
Internal reference mode. V
each with a 0.33µF capacitor.
Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to
REFIN. V
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference
sources. V
REFN, and COM each with a 0.33µF capacitor.
) sets the reference oper-
= V
REFP
COM
is internally generated
to V
= V
REF
DD
Configurations
REF
DD
/2, V
and V
DD
/2. Bypass REFP,
DD
= V
REF
/2 ±10%, drive
is internally generated to be V
/2 - V
/2 ±0.2V. V
DD
REFP
is the difference between the externally applied V
REFN
/2, V
REFIN
= V
REFP
DD
. The
DD
REF
REF
REF
/4.
or
/2
=
is internally generated to be 0.512V. Bypass REFP, REFN, and COM
V
(V
each with a 0.33µF capacitor.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
CLK accepts a CMOS-compatible signal level. Since
the interstage conversion of the device depends on the
repeatability of the rising and falling edges of the exter-
nal clock, use a clock with low jitter and fast rise and
fall times (<2ns). In particular, sampling occurs on the
rising edge of the clock signal, requiring this edge to
Figure 4. Unbuffered External Reference Mode Impedance
REFP
DD
REFERENCE MODE
/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM
REFIN
to (V
/2. Bypass REFP, REFN, and COM each with a
MAX1191
DD
/2 +0.256V) ±10%, and drive V
4kΩ
4kΩ
REFP
REFP
REFN
COM
and V
Clock Input (CLK)
62.5µA
0µA
62.5µA
REFN
. Bypass REFP,
1.75V
1.5V
1.25V
REFN
to