MAX19505ETM+ Maxim Integrated Products, MAX19505ETM+ Datasheet
MAX19505ETM+
Specifications of MAX19505ETM+
Related parts for MAX19505ETM+
MAX19505ETM+ Summary of contents
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... Reversible Bit Order (Programmable) o Data Output Test Patterns o Small, 7mm x 7mm 48-Pin Thin QFN Package with Exposed Pad PART MAX19505ETM+ + Denotes a lead(Pb)-free/RoHS-compliant package Exposed pad. Pin Configuration appears at end of data sheet. SPI is a trademark of Motorola, Inc. Features Ordering Information ...
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Dual-Channel, 8-Bit, 65Msps ADC ABSOLUTE MAXIMUM RATINGS OVDD, AVDD to GND............................................-0.3V to +3.6V CMA, CMB, REFIO, INA+, INA-, INB+, INB- to GND ......................................................-0.3V to +2.1V CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN to GND ..........-0.3V to the lower of (V ...
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ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL DYNAMIC PERFORMANCE Small-Signal Noise Floor Signal-to-Noise Ratio ...
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Dual-Channel, 8-Bit, 65Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL INTERCHANNEL CHARACTERISTICS Crosstalk ...
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ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL CLOCK INPUT (SYNC) Allowable Logic Swing Sync ...
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Dual-Channel, 8-Bit, 65Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL POWER-MANAGEMENT CHARACTERISTICS Wake-Up ...
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ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL POWER REQUIREMENTS Analog Supply Voltage Digital Output ...
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Dual-Channel, 8-Bit, 65Msps ADC ( 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω +25°C, unless otherwise noted.) A 3MHz INPUT FFT PLOT 2.99877166MHz IN - -0.493dBFS IN SNR ...
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V = 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω +25°C, unless otherwise noted.) A SINGLE-ENDED PERFORMANCE vs. INPUT FREQUENCY 85 80 SFDR1 SFDR2 -THD SINAD 55 SNR 50 45 ...
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Dual-Channel, 8-Bit, 65Msps ADC ( 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω +25°C, unless otherwise noted.) A ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE ...
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V = 1.8V, internal reference, differential clock, V AVDD OVDD = 50Ω +25°C, unless otherwise noted.) A OFFSET ERROR vs. TEMPERATURE 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40 - ...
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Dual-Channel, 8-Bit, 65Msps ADC PIN NAME 1, 12, 13, 48 AVDD Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF. 2 CMA Channel A Common-Mode Input-Voltage Reference 3 INA+ Channel A Positive ...
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PIN NAME 40 D5A Channel A Three-State Digital Output, Bit 5 41 D6A Channel A Three-State Digital Output, Bit 6 42 D7A Channel A Three-State Digital Output, Bit 7 (MSB) 43 DORA Channel A Data Over Range 44 DCLKA Channel ...
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Dual-Channel, 8-Bit, 65Msps ADC INA+ T/H INA- CMA REFIO CMB INB+ T/H INB- CLK+ CLK- SYNC CS SERIAL PORT SCLK SDIN CONTROL REGISTERS SPEN Figure 2. Functional Diagram CMA INA+ 2kΩ 2kΩ INA- SAMPLING CLOCK *V PROGRAMMABLE FROM 0.45V TO ...
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INTERNAL GAIN—BYPASS REFIO EXTERNAL GAIN CONTROL—DRIVE REFIO REFIO 1.250V 10kΩ BANDGAP SCALE AND BUFFER REFERENCE LEVEL SHIFT Figure 4. Simplified Reference Schematic Table 1. Parallel-Interface Pin Functionality SPEN SDIN/FORMAT 0 SDIN AVDD 1 Unconnected ...
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Dual-Channel, 8-Bit, 65Msps ADC CS SCLK SDIN R R WRITE 1 = READ Figure 6. Serial-Interface Communication Cycle t CSS CS SCLK SDIN Figure 7. Serial-Interface Timing Diagram Serial Programming Interface A serial interface programs ...
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Register address 0Ah is a special-function register. Writing data 5Ah to register 0Ah initiates a register reset. When this operation is executed, all control registers Table 2. Register 0Ah Status Byte BIT NO. VALUE 7 0 Reserved 6 0 Reserved ...
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Dual-Channel, 8-Bit, 65Msps ADC In addition to power management, the HPS_SHDN1 and HPS_SHDN0 activate an A+B adder mode. In this mode, the results from both channels are averaged. Control Bits: HPS_SHDN0 STBY_SHDN0 HPS_SHDN1 STBY_SHDN1 ...
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Digital Output Power Management (02h) BIT 7 BIT Bit 7–4 Don’t care Bit 3, 2 PD_DOUT_1, PD_DOUT_0: Power-down digital output state control 00 = Digital output three state (default Digital output low 10 = Digital ...
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Dual-Channel, 8-Bit, 65Msps ADC Data/DCLK Timing (03h) BIT 7 BIT 6 BIT 5 DA_BYPASS DLY_HALF_T DCLKTIME_2 Bit 7 DA_BYPASS: Data aligner bypass 0 = Nominal 1 = Bypasses data aligner delay line to minimize output data latency with respect to ...
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CHA Data Output Termination Control (04h) BIT 7 BIT 6 BIT CT_DCLK_2_A Bit 7, 6 Don’t care Bit CT_DCLK_2_A, CT_DCLK_1_A, CT_DCLK_0_A: CHA DCLK termination control 000 = 50Ω (default) 001 = 75Ω 010 = ...
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Dual-Channel, 8-Bit, 65Msps ADC Clock Divide/Data Format/Test Pattern (06h) BIT 7 BIT 6 TEST_PATTERN TEST_DATA FORMAT_1 Bit 7 TEST_PATTERN: Test pattern selection 0 = Ramps from 0 to 255 (offset binary) and repeats (subsequent formatting applied) (default Data ...
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Common Mode (08h) BIT 7 BIT 6 CMI_SELF_B CMI_ADJ_2_B CMI_ADJ_1_B CMI_ADJ_0_B Bit 7 CMI_SELF_B: CHB connect input common-mode to analog inputs 0 = Internal common-mode voltage is NOT applied to inputs (default Internal common-mode voltage applied to analog ...
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Dual-Channel, 8-Bit, 65Msps ADC 100Ω TERMINATION (PROGRAMMABLE) CLK+ AVDD 5kΩ 50Ω 10kΩ 20kΩ 50Ω THRESHOLD 5kΩ GND CLK- SELF-BIAS TURNED OFF FOR SINGLE-ENDED CLOCK OR POWER-DOWN. Figure 8. Simplified Clock Input Schematic SAMPLING INSTANT t AD IN_ SAMPLE ON RISING ...
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SAMPLING INSTANT IN_ SAMPLE ON RISING EDGE SAMPLE CLOCK t DD CHB DATA, DOR n-10 DCLK SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-. MUX_CH (BIT 2, OUTPUT FORMAT 01h) DETERMINES THE ...
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Dual-Channel, 8-Bit, 65Msps ADC SUV SYNC INPUT CLK (0) (1) 1x DIVIDED CLK (STATE) (1) ( SUV SYNC INPUT CLK (0) (1) (2) (1) (2) (3) 1x DIVIDED ...
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HO t SUV SYNC INPUT CLK (0) (1) 1x DIVIDED CLK (STATE) (1) ( SUV SYNC INPUT CLK (0) (1) (2) (1) (2) (3) 1x DIVIDED CLK (STATE) (2) (3) ...
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Dual-Channel, 8-Bit, 65Msps ADC Table 4. Data Timing Controls DATA TIMING CONTROL Data aligner bypass. When this control is active (high), data and DCLK delay is reduced by DA_BYPASS approximately 3.4ns (relative to DA_BYPASS = 0). When this control is ...
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FACTORY-DEFAULT NOMINAL DATA TIMING vs. SAMPLE RATE 2 1.8V OVDD DA_BYPASS = 1 1.5 1.0 0 SAMPLING RATE (Msps) Figure 13. Default Data Timing (V OVDD FACTORY-DEFAULT NOMINAL DATA TIMING vs. SAMPLING RATE 2.0 ...
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Dual-Channel, 8-Bit, 65Msps ADC Table 7. Recommended Timing Adjustments (V SAMPLING RATE (Msps) FROM Table 8. Allowed Settings of DCLKTIME and DTIME for DA_BYPASS = 1 DTIME<2:0> 111 (-3T/16) 111 (-3T/16) 110 (-2T/16) 110 (-2T/16); 111 (-3T/16) ...
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AVDD (PINS 1, 12, 13, 48) REFERENCE GND Figure 17. Integrated Voltage Regulator 36.5Ω 0.1µF 0. N.C. N.C. 0.1µ 36.5Ω MINI-CIRCUITS 0.5% ADT1-1WT Figure 18. Transformer-Coupled Input Drive for Input Frequencies ...
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Dual-Channel, 8-Bit, 65Msps ADC V IN 0.1µF MAX4108 100Ω 0.1µF 100Ω 0.1µF Figure 20. Single-Ended, AC-Coupled Input Drive The circuit of Figure 19 also converts a single-ended input signal to a fully differential signal. Figure 19 uti- lizes an additional ...
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Small-Signal Noise Floor (SSNF) SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone ...
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Dual-Channel, 8-Bit, 65Msps ADC TOP VIEW D2A D3A D4A D5A D6A D7A DORA DCLKA SDIN/FORMAT SCLK/DIV CS/OUTSEL AVDD For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 © 2010 Maxim Integrated Products ...