MAX19505ETM+ Maxim Integrated Products, MAX19505ETM+ Datasheet - Page 30

• Manufacturer Part Number: MAX19505ETM+
• Description: IC ADC 8BIT 1CH 65MSPS 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19505ETM+

• Number Of Bits: 8
• Sampling Rate (per Second): 65M
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 99mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual-Channel, 8-Bit, 65Msps ADC
Table 7. Recommended Timing Adjustments (V
Table 8. Allowed Settings of DCLKTIME and DTIME for DA_BYPASS = 1
Table 9. Reset Methods
The MAX19505 includes an integrated self-sensing lin-
ear voltage regulator on the analog supply (AVDD). See
Figure 17. When the applied voltage on AVDD is below
2V, the voltage regulator is bypassed, and the core
analog circuitry operates from the externally applied
voltage. If the applied voltage on AVDD is higher than
2V, the regulator bypass switches off, and voltage reg-
ulator mode is enabled. When in voltage regulation
mode, the internal-core analog circuitry operates from a
stable 1.8V supply voltage provided by the regulator.
The regulator provides an output voltage of 1.8V over a
2.3V to 3.5V AVDD input-voltage range. Since the
power-supply current is constant over this voltage
range, analog power dissipation is proportional to the
applied voltage.
30
111 (-3T/16)
110 (-2T/16)
101 (-1T/16)
000 (nominal)
001 (+1T/16)
010 (+2T/16)
011 (+3T/16)
Power-On Reset
Software Reset
Hardware Reset A register reset is initiated by the falling edge on the SHDN pin when SPEN is high.
RESET MODE
DTIME<2:0>
SAMPLING RATE (Msps)
______________________________________________________________________________________
FROM
30
Upon power-up (AVDD supply voltage and clock signal applied), the POR (power-on-reset) circuit initiates a
register reset.
Write data 5Ah to address 0Ah to initiate register reset.
Integrated Voltage Regulator
111 (-3T/16)
110 (-2T/16); 111 (-3T/16)
101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
011 (+3T/16); 010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
TO
65
DA_BYPASS
1
ALLOWED DCLKTIME<2:0> SETTINGS
DLY_HALF_T
DESCRIPTION
The user-programmable register default settings and
other factory-programmed settings are stored in non-
volatile memory. Upon device power-up, these values are
loaded into the control registers. This operation occurs
after application of supply voltage to AVDD and applica-
tion of an input clock signal. The register values are
retained as long as AVDD is applied. While AVDD is
applied, the registers can be reset, which overwrites all
user-programmed registers with the default values. This
reset operation can be initiated by software command
through the serial-port interface or by hardware control
using the SPEN and SHDN inputs. The reset time is pro-
portional to the ADC clock period and requires 130µs at
65Msps. Table 9 summarizes the reset methods.
0
OVDD
V
= 3.3V)
OVDD
= 3.3V
DTIME<2:0>
000
Power-On and Reset
DCLKTIME<2:0>
000