MAX1296BEEG+ Maxim Integrated Products, MAX1296BEEG+ Datasheet - Page 10

• Manufacturer Part Number: MAX1296BEEG+
• Description: IC ADC 12BIT 420KSPS 24-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1296BEEG+

• Number Of Bits: 12
• Sampling Rate (per Second): 420k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 762mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Number Of Adc Inputs: 2
• Architecture: SAR
• Conversion Rate: 420 KSPs
• Resolution: 12 bit
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
*Channels CH2–CH5 apply to MAX1294 only.
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
*Channels CH2–CH5 apply to MAX1294 only.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
the end of the acquisition interval, the T/H switch
opens, retaining charge on C
signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(V
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Internal protection diodes, which clamp the analog
input to V
swing within (GND - 300mV) to (V
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V
less than (GND - 50mV).
10
A2
______________________________________________________________________________________
A2
0
0
0
0
1
1
0
0
0
0
1
1
DD
and GND, allow each input channel to
HOLD
A1
0
0
1
1
0
0
A1
0
0
1
1
0
0
from the positive input (IN+) to the
IN
Analog Input Protection
+ - V
A0
0
1
0
1
0
1
HOLD
IN
A0
0
1
0
1
0
1
-)] charge from C
DD
as a sample of the
+ 300mV) without
DD
CH0
+
+ 50mV) or be
CH0
+
HOLD
HOLD
CH1
+
. At
CH1
+
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
The MAX1294/MAX1296 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next on ris-
ing edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive input “-”, and the difference of
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and C
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
CH2*
+
CH2*
+
CH3*
+
CH3*
+
-
CH4*
+
CH4*
|
(IN+) - (IN-)
+
CH5*
-
+
Track/Hold
CH5*
|
COM
is sam-
+
-
-
-
-
-
-
-
HOLD