LTC2433-1IMS#TR Linear Technology, LTC2433-1IMS#TR Datasheet - Page 14

• Manufacturer Part Number: LTC2433-1IMS#TR
• Description: IC CONV A/D 16BIT DIFF 10-MSOP
• Manufacturer: Linear Technology

Specifications of LTC2433-1IMS#TR

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC2433-1
APPLICATIO S I FOR ATIO
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 19th rising edge of SCK. On the 19th
falling edge of SCK, the device begins a new conversion.
14
(EXTERNAL)
SDO
SCK
SLEEP
CS
OUTPUT
DATA
BIT 0
EOC
U
CONVERSION
Hi-Z
TEST EOC
U
Hi-Z
TEST EOC (OPTIONAL)
Figure 7. External Serial Clock, Reduced Data Output Length
SLEEP
W
ANALOG INPUT RANGE
SLEEP
–0.5V
Hi-Z
REF
U
0.1V TO V
REFERENCE
BIT 18
TO 0.5V
EOC
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
BIT 17
1
2
3
4
5
6
“O”
V
REF
REF
IN
IN
GND
CC
SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
19th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for abort-
ing an invalid conversion cycle or synchronizing the start
of a conversion.
LTC2433-1
+
–
+
–
BIT 16
SDO
SCK
SIG
CS
F
O
10
9
8
7
DATA OUTPUT
BIT 15
MSB
3-WIRE
SPI INTERFACE
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
BIT 14
50Hz/60Hz REJECTION
BIT 5
BIT 4
CONVERSION
Hi-Z
TEST EOC
24331fa
24331 F07