LTC2412IGN Linear Technology, LTC2412IGN Datasheet - Page 31

• Manufacturer Part Number: LTC2412IGN
• Description: IC CONV A/D 24B 2CH DIFF 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2412IGN

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filtering.
The noise of the driving amplifier referred to the converter
input and including all these effects can be calculated as
N = n
LTC2412 input) can now be obtained by summing as
square root of sum of squares the three ADC input referred
noise sources: the LTC2412 internal noise (800nV), the
noise of the IN
driving amplifier.
If the F
f
x-axis is scaled by f
ratio f
decrease, but in the same time the LTC2412 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2412 significantly
simplifies antialiasing filter requirements.
The Sinc
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (f
LTC2412’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode sig-
nal filtering both in the analog and digital domain. Inde-
pendent of the operating mode, f
f
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, f
60Hz notch setting f
mode, f
The combined normal mode rejection performance is
shown in Figure 33 for the internal oscillator with 50Hz
notch setting (F
oscillator with 60Hz notch setting (F
external oscillator mode. The regions of low rejection
occurring at integer multiples of f
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 35 (rejection near DC) and
EOSC
OUTMAX
, Figure 32 can still be used for noise calculation if the
i
EOSC
O
• freq
S
pin is driven by an external oscillator of frequency
4
where f
= f
digital filter provides greater than 120dB normal
/153600, the Figure 32 plot accuracy begins to
EOSC
i
+
. The total system noise (referred to the
O
driving amplifier and the noise of the IN
N
/10.
= HIGH) and in Figure 34 for the internal
in the notch frequency and f
U
S
EOSC
= 15360Hz. In the external oscillator
/153600. For large values of the
U
S
S
S
= 12800Hz and with a
W
O
= 256 • f
have a very narrow
= LOW) and for the
N
U
OUTMAX
= 2048 •
S
). The
is
–
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
100
0.1
–100
–110
–120
10
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
1
–10
–20
–30
–40
–50
–60
–70
–80
–90
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
0.1
0
0
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 f
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
INPUT NOISE SOURCE SINGLE POLE
1
S
f
S
F
EQUIVALENT BANDWIDTH (Hz)
O
2f
2f
= HIGH
S
10
S
3f
S
3f
4f
S
100
S
4f
F
F
5f
O
O
S
S
= LOW
= HIGH
5f
6f
1k
S
S
7f
6f
S
S
10k 100k
8f
7f
S
S
9f
S
8f
10f
S
2412 F32
S
9f
11f
LTC2412
2412 F34
2412 F33
S
1M
S
10f
12f
S
S
F
F
OSCILLATOR,
f
EOSC
O
O
= LOW OR
= EXTERNAL
= 10 • f
31
S
2412f