LTC1594IS#TRPBF Linear Technology, LTC1594IS#TRPBF Datasheet - Page 13

• Manufacturer Part Number: LTC1594IS#TRPBF
• Description: IC A/D CONV 12BIT SRL 4CH 16SOIC
• Manufacturer: Linear Technology

Specifications of LTC1594IS#TRPBF

• Number Of Bits: 12
• Sampling Rate (per Second): 16.8M
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.6mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS
Operation with D
The LTC1594/LTC1598 can be operated with D
D
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire.
The processor pin connected to this data line should be
configurable as either an input or an output. The LTC1594/
LTC1598 will take control of the data line after CS falling
and before the 6th falling CLK while the processor takes
control of the data line when CS is high (see Figure 3).
COM = GND
DATA (D
OUT
MUXOUT
ADCIN =
CSMUX
CH0 TO
CSADC
D
CLK
CH7
OUT
D
IN
IN
/D
tied together. This eliminates one of the lines
CLK
OUT
CS
)
EN
D2
Hi-Z
D1
IN
U
D0
and D
t
SMPL
t
ON
INFORMATION
t
suCS
U
OUT
MPU CONTROLS DATA LINE AND SENDS
NULL
MUX ADDRESS TO LTC1594/LTC1598
BIT
EN
Figure 3. LTC1594/LTC1598 Operation with D
1
B11
Tied Together
Figure 4. Select Certain Channel Once for Mulitple Conversions
B10
W
B9
D2
2
DON’T CARE
B8
PROCESSOR MUST RELEASE DATA
B7
t
CONV
BEFORE THE 6TH FALLING CLK
B6
LINE AFTER CS FALLING AND
D1
B5
U
3
B4
IN
B3 B2
and
4
B1 B0
Therefore the processor port line must be switched to an
input with CS being low to avoid a conflict.
Separate Chip Selects for MUX and ADC
The LTC1594/LTC1598 provide separate chip selects,
CSMUX and CSADC, to control MUX and ADC separately.
This feature not only provides the flexibility to select a
particular channel once for multiple conversions (see
Figure 4) but also maximizes the sample rate up to
20ksps (see Figure 5).
D0
D0
Hi-Z
t
SMPL
5
IN
t
suCS
t
and D
NULL
suCS
BIT
B11
OUT
B10
6
Tied Together
B9
DON’T CARE
B8
B7
t
LTC1594/LTC1598 CONTROLS DATA LINE AND SENDS
CONV
LTC1594/LTC1598 TAKES CONTROL OF DATA
LINE AFTER CS FALLING AND BEFORE THE
6TH FALLING CLK
LTC1594/LTC1598
B6
B5
A/D RESULT BACK TO MPU
B4
B11
B3 B2
B1 B0
B10
Hi-Z
13
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