LTC2415-1IGN#TR Linear Technology, LTC2415-1IGN#TR Datasheet - Page 36

• Manufacturer Part Number: LTC2415-1IGN#TR
• Description: IC ADC 24BIT DIFFINPUT/REF16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2415-1IGN#TR

• Number Of Bits: 24
• Sampling Rate (per Second): 13.75
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC2415-1IGNTR

LTC2415/LTC2415-1
36
TYPICAL APPLICATIO S
************************************************************
* This example program transfers the LTC2415/LTC2415-1 32-bit output *
* conversion result into four consecutive 8-bit memory locations.
************************************************************
*68HC11 register definition
PORTD
*
DDRD
SPSR
*
SPSR
*
SPDR
*
* RAM variables to hold the LTC2415/LTC2415-1’s 32 conversion result
*
DIN1
DIN2
DIN3
DIN4
*
**********************
* Start GETDATA Routine *
**********************
*
INIT1
*
*
*DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
*
*
*
*
GETDATA PSHX
*
*
*
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
ORG
LDS
LDAA
STAA
LDAA
STAA
LDAA
STAA
PSHY
PSHA
LDX
LDY
BCLR
$1008
$1009
$1028
$1029
$102A
$00
$01
$02
$03
$C000
#$CFFF
#$2F
PORTD
#$38
DDRD
#$50
SPCR
#$0
#$1000
PORTD, Y %00100000
Port D data register
" – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD"
Port D data direction register
SPI control register
"SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0"
SPI status register
"SPIF,WCOL, – ,MODF; – , – , – , – "
SPI data register; Read-Buffer; Write-Shifter
This memory location holds the LTC2415/LTC2415-1’s bits 31 - 24
This memory location holds the LTC2415/LTC2415-1’s bits 23 - 16
This memory location holds the LTC2415/LTC2415-1’s bits 15 - 08
This memory location holds the LTC2415/LTC2415-1’s bits 07 - 00
Program start location
Top of C page RAM, beginning location of stack
–,–,1,0;1,1,1,1
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
–,–,1,1;1,0,0,0
SS*, SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher E-
Clock frequencies, change the above value of $50 to a value
that ensures the SCK frequency is 2MHz or less.)
The X register is used as a pointer to the memory locations
that hold the conversion data
U
This sets the SS* output bit to a logic
low, selecting the LTC2415/LTC2415-1
*
sn2415 24151fs