LTC2415-1CGN Linear Technology, LTC2415-1CGN Datasheet
LTC2415-1CGN
Specifications of LTC2415-1CGN
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LTC2415-1CGN Summary of contents
Page 1
... INL, 0.23ppm RMS noise and a 2.7V to 5.5V supply range. They use delta-sigma technology and provide single cycle settling time for multiplexed applications. Through a single pin, the LTC2415 can be configured for better than 110dB input differential mode rejection at 50Hz or 60Hz 2 can be driven by an external oscillator for a user defined rejection frequency ...
Page 2
... C. (Notes – REF = GND, CC – TOP VIEW ORDER PART NUMBER 16 GND LTC2415CGN 15 GND LTC2415IGN LTC2415-1CGN 13 SCK LTC2415-1IGN 12 SDO PART MARKING 10 GND 2415 9 GND 2415I GN PACKAGE 24151 24151I = 125 C/W JA MIN TYP MAX ...
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... Input Common Mode Rejection 2.5V REF 49Hz to 61.2Hz (LTC2415-1) GND IN Input Normal Mode Rejection F = GND O 49Hz to 61.2Hz (LTC2415-1) Input Normal Mode Rejection External Oscillator External Clock f /2560 14% EOSC (LTC2415-1) Input Normal Mode Rejection External Oscillator External Clock f /2560 4% ...
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... LTC2415/LTC2415 DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH CS Low Level Input Voltage IL CS High Level Input Voltage IH SCK V Low Level Input Voltage IL SCK I Digital Input Current IN CS Digital Input Current ...
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... ISCK f External SCK Frequency Range ESCK t External SCK Low Period LESCK t External SCK High Period HESCK t Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12), LTC2415 DOUT_ISCK t External SCK 32-Bit Data Output Time (Note 9) DOUT_ESCK SDO Low SDO High Z t3 ...
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... LTC2415/LTC2415 TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error Over Temperature ( 5V) REF 106 REF V = 2.5V 106.0 INCM + REF = 5V – REF = GND 105 GND 105.0 104 –45 C 104.0 A 103.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 V (V) IN 2415 G01 Integral Nonlinearity Over ...
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... IN = 2.5V REF GND –102 REF = – REF = GND –102.5 –103.0 –103.5 –104.0 –104.5 –105.0 –105 TIME (HRS) 2415 G17 LTC2415/LTC2415-1 Noise Histogram (Output Rate = 105Hz 5V 2.5V) CC REF 15 GAUSSIAN DISTRIBUTION m = –206.5ppm 12 = 1.07ppm 10,000 CONSECUTIVE READINGS 2.5V REF REF = 2.5V – REF = GND ...
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... LTC2415/LTC2415 TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs V INCM 1800 + INCM – REF INCM GND 1600 REF = – REF = GND 1400 1200 1000 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V (V) INCM 2415 G19 RMS Noise vs V REF 1600 1400 1200 ...
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... REF = 2.5V –20 – REF = GND + – GND F = GND – –60 –80 –100 –120 15200 15300 15400 15500 FREQUENCY AT V (Hz) CC 2415 G35 LTC2415/LTC2415-1 – Full-Scale Error vs Temperature ( –1 –2 – –4 REF = 5V – REF = GND + IN = GND –5 – 2. GND O –6 – ...
Page 10
... LTC2415/LTC2415 TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Output Data Rate 1000 900 + REF = 5V – REF = GND 800 + IN = GND – 700 IN = GND F = EXT OSC O 600 CS = GND SCK =N/C 500 SDO = N/C 400 300 200 100 100 OUTPUT DATA RATE (READINGS/SEC CTIO S GND (Pins 10, 15, 16): Ground. Multiple ground ...
Page 11
... Hi-Z OH 2415 TA03 connected to GND (F oscillator and the digital filter first null is located at 60Hz (LTC2415 only), (LTC2415) or simultaneous 50Hz/60Hz (LTC2415-1). CC When F O pin is frequency f O system clock and the digital filter first null is located at a frequency f W ADC Figure 1. Functional Block Diagram ...
Page 12
... The LTC2415/LTC2415-1 incorporate a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2415 achieves a minimum of 110dB rejection at the line frequency (50Hz or 60Hz LTC2415-1 achieves a minimum of 87db rejection at 50Hz 2% and 60Hz 2% simultaneously. ...
Page 13
... Based on the LTC2415/ REF LTC2415-1 new modulator architecture, the temperature drift of the offset is less then 0.01ppm/ C. More informa- tion on the LTC2415/LTC2415-1 offset is described in the Offset Accuracy and Drift section of this data sheet. Power-Up Sequence The LTC2415/LTC2415-1 automatically enter an internal reset state when the power supply voltage V below approximately 2 ...
Page 14
... Offset Accuracy and Drift Unlike the LTC2410/LTC2413 and the entire LTC2400 fam- ily, the LTC2415/LTC2415-1 do not perform an offset DMY SIG MSB calibration every cycle. The reason for this is to increase the ...
Page 15
... Figure 4), several characteristics of this CC variation can be used to eliminate the effects. First, the variation with respect to supply voltage is linear. Second, the magnitude of the offset error decreases with de- creased supply voltage. Third, the offset error increases Table 2. LTC2415/LTC2415-1 Output Data Format Differential Input Voltage 0.5 • ...
Page 16
... When a fundamental rejection frequency different from the range 49Hz to 61.2Hz is required or when the converter must be synchronized with an outside source, the LTC2415-1 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the F oscillator. The frequency least 2560Hz to be detected ...
Page 17
... O Frequency f External Serial Clock with Frequency Serial Interface Pins The LTC2415/LTC2415-1 transmit the conversion results and receive the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the . O converter status and during the data output state it is used to read the conversion result. – ...
Page 18
... SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2415/LTC2415-1 create their own se- rial clock by dividing the internal conversion clock the External SCK mode of operation, the SCK pin is used as input ...
Page 19
... Independent of CS, the device automatically enters the sleep state once the con- version is complete. While in the sleep state high, the LTC2415/LTC2415-1 power consumption is reduced by an order of magnitude When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift regis- ter ...
Page 20
... SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time t (if EOC = during the falling edge of EOC). The value of t (LTC2415 (LTC2415-1) if the device is using its internal oscillator ( 50Hz REJECTION (LTC2415) ...
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... BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 SIG MSB DATA OUTPUT Figure 11. Internal Serial Clock, Single Cycle Operation LTC2415/LTC2415 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 2-WIRE INTERFACE BIT 5 BIT 0 LSB 24 CONVERSION 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR 10k = 60Hz REJECTION (LTC2415) ...
Page 22
... LTC2415/LTC2415 APPLICATIO S I FOR ATIO by an external oscillator of (LTC2415-1) frequency f then t is 3.6 pulled HIGH before time EOCtest EOSC t , the device remains in the sleep state. The conver- EOCtest sion result is held in the internal static shift register remains LOW longer than t EOCtest edge of SCK will occur and the conversion result is serially shifted out of the SDO pin ...
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... REF 6 11 – 10, 15, 16 GND BIT 29 BIT 28 BIT 27 BIT 26 SIG MSB DATA OUTPUT Figure 13. Internal Serial Clock, Continuous Operation LTC2415/LTC2415 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 2-WIRE INTERFACE BIT 5 BIT 0 LSB 24 CONVERSION sn2415 24151fs 23 2415 F13 ...
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... REF REF 6 11 – 10, 15, 16 GND BIT 31 BIT 30 EOC DATA OUTPUT SLEEP Figure 14. Internal Serial Clock, Autostart Operation 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 2-WIRE INTERFACE C EXT BIT 29 BIT 0 SIG Hi-Z CONVERSION 2415 F14 sn2415 24151fs ...
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... LTC2415 66.6ms and the conversion time of the LTC2413 is 146ms, while the LTC2415-1 is 73ms. In systems where the SDO pin is monitored for the end-of-conversion signal (SDO goes low once the conversion is complete) these two devices can be interchanged. In cases where SDO is not monitored, a wait state is inserted between conversions, the duration of this wait state must be greater than 66 ...
Page 26
... LTC2415-1’s front end is clocked at 69900Hz corre- sponding to 14.2 s. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 14 = 1.01 s (LTC2415-1).. When an external oscillator of frequency f and, for a settling error of less than 1ppm, Input Current If complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current ...
Page 27
... SW REF I LEAK Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter. Figure 18 shows the mathematical expressions for the average bias currents + – ...
Page 28
... When F = LOW (internal oscillator and 60Hz notch), the O typical differential input resistance is 1.8M (LTC2415), 1.97M (LTC2415-1) which will generate a gain error of approximately 0.28ppm for each ohm of source resis- + – tance driving ...
Page 29
... –120 0 0.5 1 1.5 2 2.5 3 3 (V) INCM +400 +200 +100 – and Input Source Resistance Imbalance = R + – R –) for Large C SOURCEIN SOURCEIN LTC2415/LTC2415 0. –60 –120 –180 REF = 5V – REF = GND + IN = 1.25V – 3.75V –240 F = GND –300 0 100 200 300 400 500 600 700 800 900 1000 ...
Page 30
... LTC2415/LTC2415 APPLICATIO S I FOR ATIO Reference Current In a similar fashion, the LTC2415/LTC2415-1 sample the + differential reference pins REF and REF small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance ...
Page 31
... When F = LOW (internal oscillator and 60Hz notch), every O 100 of source resistance driving REF into about 1.34ppm additional INL error. For the LTC2415, when F = HIGH (internal oscillator and 50Hz notch), every O 100 of source resistance driving REF into about 1.1ppm additional INL error ...
Page 32
... LTC2415-1 offers simultaneous rejection of 50Hz and 60Hz by tying F low. This sets the notch O frequency to approximately 55Hz (see Figure 32 notch frequency of 55Hz, the LTC2415-1 rejects 50Hz 2% and 60Hz 2% better than 72dB. In order to achieve better than 87dB rejection of both 50Hz and 60Hz 2 ...
Page 33
... SPI data transfer between the controller and the LTC2415/LTC2415-1. Figure 36 shows the simple 3-wire SPI connection. Figure 35. Use a Differential Multiplexer to Expand Channel Capability Figure 36. Connecting the LTC2415/LTC2415 68HC11 MCU Using the SPI Serial Interface W U The code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. This is followed by initializing PORT D’ ...
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... The LTC2415/LTC2415-1 have the virtue of being able to digitize an input voltage that is outside the range defined by the reference, thereby providing a simple means to implement a ratiometric example of correlated double sampling. This circuit uses a bipolar amplifier (LT1219— ...
Page 35
... R5 4 499 1000pF 61.9 0.1% 100 Q1: SILICONIX Si9802DY MMBD2907 Q2, Q3: Q4, Q5: MMBD3904 LTC2415/LTC2415-1 10V 0 LT1219 2 – SHDN 0 10k C3 2.2nF C4 2.2nF R6 10k 10V 0 – LT1219 0.1 F SHDN (800) 554-5565 30pF 30pF – IN LTC2415/ LTC2415 REF 4 – REF GND 2415 F37 sn2415 24151fs 35 ...
Page 36
... This memory location holds the LTC2415/LTC2415-1’s bits DIN2 EQU $01 This memory location holds the LTC2415/LTC2415-1’s bits DIN3 EQU $02 This memory location holds the LTC2415/LTC2415-1’s bits DIN4 EQU $03 This memory location holds the LTC2415/LTC2415-1’s bits ********************** * Start GETDATA Routine * ...
Page 37
... PORTD,Y %00100000 This sets the SS* output bit to a logic high, * de-selecting the LTC2415/LTC2415-1 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 38. This is an Example of 68HC11 Code That Captures the LTC2415/LTC2415-1 Conversion Results Over the SPI Serial Interface Shown in Figure LTC2415/LTC2415-1 sn2415 24151fs 37 ...
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... LTC2415/LTC2415-1 U TYPICAL APPLICATIO S U PCB LAYOUT A D FIL LTC2415CGN Differential Input 24-Bit ADC with 2 Output Rate Demo Circuit DC382 www.linear-tech.com LTC Confidential For Customer Use Only Silkscreen Top 38 Figure 39. Display Graphic W Top Layer sn2415 24151fs ...
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... BSC LTC2415/LTC2415-1 0.189 – 0.196* (4.801 – 4.978) (0.229 0.229 – 0.244 0.150 – 0.157** (5.817 – 6.198) (3.810 – 3.988) ...
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... U3D R5 R6 74HC14 49 22k 3 Q1 MMBT3904LT1 2 R8 51k V CC BYPASS CAP C7 FOR U3 0.1 F 2415 F40 Noise P-P Noise, Pin Compatible with LTC2415 RMS Noise, 4ppm INL RMS Noise RMS LT/TP 0202 2K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2001 sn2415 24151fs ...