LTC1409CSW Linear Technology, LTC1409CSW Datasheet - Page 18

• Manufacturer Part Number: LTC1409CSW
• Description: IC A/D CONV 12BIT SAMPLNG 28SOIC
• Manufacturer: Linear Technology

Specifications of LTC1409CSW

• Number Of Bits: 12
• Sampling Rate (per Second): 800k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1409
18
A
PPLICATI
Figure 14b. SHDN to CONVST Wake-Up Timing
NAP/SLP
CONVST
CONVST
Figure 15. CS to CONVST Setup Timing
SHDN
Figure 14a. NAP/SLP to SHDN Timing
SHDN
RD
CS
O
U
t
S
3
t
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
1
t
4
t
2
I FOR ATIO
CONVST
U
BUSY
DATA
W
LTC1409 • F14a
LTC1409 • F14b
LTC1409 • F15
DB11 TO DB0
DATA (N – 1)
t
6
t
5
t
CONV
U
)
t
7
t
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 18) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
In slow memory and ROM modes (Figures 19 and 20) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor applies a logic low to
RD (= CONVST) starting the conversion. BUSY goes low
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
8
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
LTC1409 • F16