LTC1415CSW#TRPBF Linear Technology, LTC1415CSW#TRPBF Datasheet - Page 4

IC A/D CONV 12BIT SAMPLNG 28SOIC

LTC1415CSW#TRPBF

Manufacturer Part Number
LTC1415CSW#TRPBF
Description
IC A/D CONV 12BIT SAMPLNG 28SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1415CSW#TRPBF

Number Of Bits
12
Sampling Rate (per Second)
1.25M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
100mW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1415CSW#TRPBFLTC1415CSW
Manufacturer:
LT/凌特
Quantity:
20 000
TI I G CHARACTERISTICS
LTC1415
The
temperature range; all other limits and typicals T
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above V
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above V
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below ground without latchup. These pins are not clamped
to V
Note 5: V
specified.
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
4
SAMPLE(MAX)
CONV
ACQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
W U
DD
.
denotes specifications which apply over the full operating
DD
= 5V, f
PARAMETER
Maximum Sampling Frequency
Conversion and Acquisition Time
Conversion Time
Acquisition Time
CS to RD Setup Time
CS to CONVST Setup Time
NAP/SLP to SHDN Setup Time
SHDN to CONVST Wake-Up Time Nap Mode (Note 10)
CONVST Low Time
CONVST to BUSY Delay
Data Ready Before BUSY
Delay Between Conversions
Wait Time RD After BUSY
Data Access Time After RD
Bus Relinquish Time
RD Low Time
CONVST High Time
Aperture Delay of Sample-and-Hold
SAMPLE
= 1.25MHz, t
r
= t
f
= 5ns unless otherwise
A
= 25 C.
DD
CONDITIONS
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
Sleep Mode, C
(Notes 10, 11)
C
(Note 10)
(Note 10)
C
C
0 C = T
– 40 C = T
L
L
L
without latchup.
= 25pF
= 25pF
= 100pF
(Note 5)
A
= 70 C
A
= 85 C
DD
REFCOMP
,
= 10 F (Note 10)
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 425ns after the start of the conversion or after BUSY rises.
Note 12: CS = RD = CONVST = 0V.
IN
input with – A
IN
grounded.
1.25
MIN
– 5
t
10
50
20
15
50
50
0
10
– 1.5
TYP
200
200
10
10
35
20
25
10
MAX
800
700
150
60
35
45
45
60
30
35
40
UNITS
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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