LTC2224CUK Linear Technology, LTC2224CUK Datasheet - Page 14

• Manufacturer Part Number: LTC2224CUK
• Description: IC ADC 12BIT 135MSPS SAMPL 48QFN
• Manufacturer: Linear Technology

Specifications of LTC2224CUK

• Number Of Bits: 12
• Sampling Rate (per Second): 135M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 680mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2224
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
should be driven with the input signal and A
connected to 1.6V or V
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The V
44) may be used to provide the common mode bias level.
V
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
ground close to the ADC with a 2.2µF or greater capacitor.
14
CM
can be tied directly to the center tap of a transformer
U
CM
U
.
CM
pin must be bypassed to
W
CM
output pin (Pin
IN
–
U
should be
IN
+
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2224 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC, the sample-
and-hold circuit will connect the 1.6pF sampling capacitor
to the input pin and start the sampling period. The sam-
pling period ends when ENC rises, holding the sampled
input on the sampling capacitor. Ideally the input circuitry
should
the sampling capacitor during the sampling period
1/(2F
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2224 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
ANALOG
INPUT
ENCODE
Figure 3. Single-Ended to Differential Conversion
0.1µF
be
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
); however, this is not always possible and the
1:1
T1
fast
Using a Transformer
25Ω
25Ω
enough
0.1µF
25Ω
25Ω
CM
, setting the ADC input
to
2.2µF
12pF
V
A
A
CM
IN
IN
+
–
fully
LTC2224
2224 F03
charge
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