LTC2240CUP-12#TRPBF Linear Technology, LTC2240CUP-12#TRPBF Datasheet - Page 6

• Manufacturer Part Number: LTC2240CUP-12#TRPBF
• Description: IC ADC 12BIT 170MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2240CUP-12#TRPBF

• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 638mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
LTC2240-12
SYMBOL
Pipeline Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
Note 4: V
ENC
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from
a “best straight line” fi t to the transfer curve. The deviation is measured
from the center of the quantization band.
TYPICAL PERFORMANCE CHARACTERISTICS
range, otherwise specifi cations are at T
6
–1.0
–0.2
–0.4
–0.6
–0.8
1.0
0.8
0.6
0.4
0.2
+
/ENC
0
0
Integral Nonlinearity
DD
–
= 2V
= 2.5V, f
1024
P-P
sine wave, input range = 2V
SAMPLE
OUTPUT CODE
PARAMETER
DATA to CLKOUT Skew
Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
2048
= 170MHz, LVDS outputs, differential
3072
224012 G01
4096
A
DD
= 25°C. (Note 4)
P-P
without latchup.
with differential
–1.0
–0.2
–0.4
–0.6
–0.8
1.0
0.8
0.6
0.4
0.2
0
The
0
Differential Nonlinearity
CONDITIONS
(t
l
DD
C
denotes the specifi cations which apply over the full operating temperature
– t
, they
1024
D
) (Note 7)
OUTPUT CODE
2048
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code fl ickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: V
sine wave, input range = 1V
Note 10: SNR minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
3072
DD
= 2.5V, f
224012 G02
(T
4096
A
= 25°C unless otherwise noted, Note 4)
SAMPLE
–100
–110
P-P
–60
–70
–10
–20
–30
–40
–50
–80
–90
= 170MHz, differential ENC
l
0
with differential drive, output C
0
8192 Point FFT, f
–1dB, 2V Range, LVDS Mode
10
MIN
–0.6
20
FREQUENCY (MHz)
30
5 and 6
TYP
0
5
5
40
IN
= 5MHz,
50
+
/ENC
MAX
0.6
60
–
LOAD
= 2V
70
224012 G03
= 5pF.
P-P
224012fc
UNITS
Cycles
Cycles
Cycles
80
ns