LTC1750IFW Linear Technology, LTC1750IFW Datasheet - Page 11

• Manufacturer Part Number: LTC1750IFW
• Description: IC ADC 14BIT 80MSPS SMPL 48TSSOP
• Manufacturer: Linear Technology

Specifications of LTC1750IFW

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.69W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
SENSE
4.7 F
A
A
PGA
V
IN
IN
CM
+
–
INPUT
REFERENCE
S/H
SELECT
RANGE
2.0V
U
REF
BUF
U
FIRST PIPELINED
ADC STAGE
(5 BITS)
W
AMP
DIFF
REF
0.1 F
REFLB
1 F
Figure 1. Functional Block Diagram
REFL
REFHA
U
4.7 F
SECOND PIPELINED
REFH
ADC STAGE
(4 BITS)
REFLA REFHB
1 F
0.1 F
INTERNAL CLOCK SIGNALS
DIFFERENTIAL
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
CONVERTER OPERATION
The LTC1750 is a CMOS pipelined multistep converter with
a front-end PGA. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized value
five cycles later, see the Timing Diagram section. The analog
input is differential for improved common mode noise
immunity and to maximize the input range. Additionally,
the differential input drive will reduce even order harmon-
ics of the sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
The LTC1750 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
LOW JITTER
DRIVER
CLOCK
ENC
INPUT
SNR
ENC
JITTER
THIRD PIPELINED
ADC STAGE
CALIBRATION LOGIC
= –20log (2 ) • F
(4 BITS)
CONTROL LOGIC
AND
MSBINV
IN
FOURTH PIPELINED
AND CORRECTION
• T
SHIFT REGISTER
ADC STAGE
DRIVERS
(4 BITS)
OUTPUT
JITTER
OGND
LTC1750
1750 F01
OV
OF
D13
D0
CLKOUT
11
DD
0.5V TO
5V
1750f