LTC2242IUP-12#TRPBF Linear Technology, LTC2242IUP-12#TRPBF Datasheet - Page 21

• Manufacturer Part Number: LTC2242IUP-12#TRPBF
• Description: IC ADC 12BIT 250MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2242IUP-12#TRPBF

• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 975mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
Data Format
The LTC2242-12 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. Connecting MODE to GND
or 1/3V
MODE to 2/3V
format. An external resistor divider can be used to set the
1/3V
states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN
0
1/3V
2/3V
V
Overfl ow Bit
An overfl ow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overfl ow or underfl ow on the
A data bus, while a logic high on the OFB pin indicates an
overfl ow or underfl ow on the B data bus. In LVDS mode,
a differential logic high on the OF
overfl ow or underfl ow.
Output Clock
The ADC has a delayed version of the ENC
as a digital output, CLKOUT. The CLKOUT pin can be used
DD
LATCH
LTC2242-12
FROM
DATA
DD
DD
OE
DD
DD
Figure 13a. Digital Output Buffer in CMOS Mode
or 2/3V
PREDRIVER
selects offset binary output format. Connecting
LOGIC
V
DD
DD
DD
or V
OUTPUT FORMAT
2’s Complement
2’s Complement
logic values. Table 3 shows the logic
Offset Binary
Offset Binary
DD
selects 2’s complement output
V
DD
+
/OF
OV
–
CYCLE STABILIZER
DD
pins indicates an
CLOCK DUTY
+
input available
43Ω
2242 F13a
Off
On
On
Off
OV
OGND
DD
TYPICAL
DATA
OUTPUT
0.1μF
0.5V
TO 2.625V
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. In
all CMOS modes, A bus data will be updated just after
CLKOUTA rises and can be latched on the falling edge of
CLKOUTA. In demux CMOS mode with interleaved update,
B bus data will be updated just after CLKOUTB rises and
can be latched on the falling edge of CLKOUTB. In demux
CMOS mode with simultaneous update, B bus data will be
updated just after CLKOUTB falls and can be latched on
the rising edge of CLKOUTB. In LVDS mode, data will be
updated just after CLKOUT
latched on the falling edge of CLKOUT
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply then OV
1.8V supply.
In the CMOS output mode, OV
any voltage up to 2.625V. OGND can be powered with any
voltage from GND up to 1V and must be less than OV
The logic outputs will swing between OGND and OV
In the LVDS output mode, OV
2.5V supply and OGND should be connected to GND.
LTC2242-12
–
+
Figure 13b. Digital Output in LVDS Mode
D
D
1.25V
10k
10k
3.5mA
DD
+
/CLKOUT
should be tied to that same
DD
DD
should be connected to a
224212 F13b
LTC2242-12
D
D
can be powered with
OUT
OUT
–
+
100Ω
DD
/CLKOUT
rises and can be
+
–
OGND
, should be tied
OV
DD
0.1μF
RECEIVER
–
21
LVDS
.
224212fb
2.5V
DD
DD
.
.