LTC2242IUP-12#TRPBF Linear Technology, LTC2242IUP-12#TRPBF Datasheet
LTC2242IUP-12#TRPBF
Specifications of LTC2242IUP-12#TRPBF
Available stocks
Related parts for LTC2242IUP-12#TRPBF
LTC2242IUP-12#TRPBF Summary of contents
Page 1
... An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts. ...
Page 2
... GND 16 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL LTC2242CUP-12#PBF LTC2242CUP-12#TRPBF LTC2242IUP-12#PBF LTC2242IUP-12#TRPBF LEAD BASED FINISH TAPE AND REEL LTC2242CUP-12 LTC2242CUP-12#TR LTC2242IUP-12 LTC2242IUP-12#TR Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi label on the shipping container. ...
Page 3
CONVERTER CHARACTERISTICS temperature range, otherwise specifi cations are at T PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise ANALOG INPUT ● The denotes the specifi cations which ...
Page 4
LTC2242-12 INTERNAL REFERENCE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance CM DIGITAL INPUTS AND DIGITAL OUTPUTS full operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER + – ...
Page 5
POWER REQUIREMENTS range, otherwise specifi cations are SYMBOL PARAMETER V Analog Supply Voltage DD P Sleep Mode Power SLEEP P Nap Mode Power NAP LVDS OUTPUT MODE OV Output Supply Voltage DD I Analog Supply Current VDD ...
Page 6
LTC2242-12 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage ...
Page 7
TYPICAL PERFORMANCE CHARACTERISTICS 8192 Point FFT 70MHz, IN –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 120 100 FREQUENCY (MHz) 224212 G04 8192 Point ...
Page 8
LTC2242-12 TYPICAL PERFORMANCE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range 30MHz, –1dB, IN LVDS Mode 90 85 SFDR SNR 100 150 200 250 SAMPLE RATE (Msps) 224212 G13 ...
Page 9
PIN FUNCTIONS (CMOS Mode (Pins 1, 2): Positive Differential Analog Input. IN – A (Pins 3, 4): Negative Differential Analog Input. IN REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip ...
Page 10
LTC2242-12 PIN FUNCTIONS (LVDS Mode) + AIN (Pins 1, 2): Positive Differential Analog Input. – AIN (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, ...
Page 11
FUNCTIONAL BLOCK DIAGRAM + A IN INPUT FIRST PIPELINED S/H ADC STAGE – 1.25V CM REFERENCE 2.2μF RANGE SELECT REF SENSE BUF SECOND PIPELINED THIRD PIPELINED ADC STAGE ADC STAGE REFH REFL INTERNAL CLOCK SIGNALS DIFFERENTIAL DIFF ...
Page 12
LTC2242-12 TIMING DIAGRAMS ANALOG N INPUT – ENC + ENC D0-D11, OF – CLKOUT + CLKOUT ANALOG INPUT – ENC + ENC DA0-DA11, OFA CLKOUTB CLKOUTA DB0-DB11, OFB 12 LVDS Output Mode Timing All Outputs Are Differential and Have LVDS ...
Page 13
TIMING DIAGRAMS ANALOG INPUT – ENC + ENC DA0-DA11, OFA DB0-DB11, OFB CLKOUTB CLKOUTA Demultiplexed CMOS Outputs with Simultaneous Update ANALOG INPUT – ENC + ENC DA0-DA11, OFA DB0-DB11, OFB CLKOUTB CLKOUTA Demultiplexed CMOS Outputs with Interleaved Update All Outputs ...
Page 14
LTC2242-12 APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen- tal input frequency and the RMS amplitude of all other frequency components at ...
Page 15
APPLICATIONS INFORMATION Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifi er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input ...
Page 16
LTC2242-12 APPLICATIONS INFORMATION driver circuit. The V pin must be bypassed to ground CM close to the ADC with a 2.2μF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dy- namic performance of ...
Page 17
APPLICATIONS INFORMATION the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequen- cies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. + – The A and A ...
Page 18
LTC2242-12 APPLICATIONS INFORMATION LTC2242-12 2Ω 1.25V 2.2μF RANGE DETECT AND CONTROL TIE TO V FOR 2V RANGE; DD SENSE TIE TO V FOR 1V RANGE; CM RANGE = 2 • V FOR SENSE REFLB 0.5V < V < ...
Page 19
APPLICATIONS INFORMATION MA/COM 0.1μF ETC1-1-13 CLOCK • INPUT 0.1μF + ENC V = 1.5V THRESHOLD – 1.5V ENC 0.1μF Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter Maximum and Minimum Encode Rates The maximum encode rate for the ...
Page 20
LTC2242-12 APPLICATIONS INFORMATION Table 1. Output Codes vs Input Voltage + – A – A D11 – (2V Range) OF (Offset Binary) >+1.000000V 1 1111 1111 1111 +0.999512V 0 1111 1111 1111 +0.999024V 0 1111 1111 1110 ...
Page 21
APPLICATIONS INFORMATION LTC2242- DATA PREDRIVER FROM LOGIC LATCH OE Figure 13a. Digital Output Buffer in CMOS Mode Data Format The LTC2242-12 parallel digital output can be selected for offset binary or 2’s complement format. The format ...
Page 22
LTC2242-12 APPLICATIONS INFORMATION Output Enable The outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are ...
Page 23
APPLICATIONS INFORMATION The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a fi lter close to the ADC may be benefi cial. This fi lter should be close to the ADC to both ...
Page 24
LTC2242-12 APPLICATIONS INFORMATION GND 16 GND 61 GND 64 GND ...
Page 25
APPLICATIONS INFORMATION Silkscreen Top Layer 1 Component Side LTC2242-12 Layer 2 GND Plane Layer 3 Power/Ground Plane 25 224212fb ...
Page 26
LTC2242-12 APPLICATIONS INFORMATION Layer 4 Power/Ground Planes Layer 5 Power/Ground Planes 26 Layer Back Solder Side Silk Screen Back, Solder Side 224212fb ...
Page 27
... PIN 1 TOP MARK (SEE NOTE 5) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. UP Package 64-Lead Plastic QFN (9mm × ...
Page 28
... High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz 12.5dB, 50Ω Single-Ended RF and LO Ports www.linear.com ● 224212fb LT 1107 REV B • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2006 ...