LTC2240IUP-12#PBF Linear Technology, LTC2240IUP-12#PBF Datasheet - Page 19

• Manufacturer Part Number: LTC2240IUP-12#PBF
• Description: IC ADC 12BIT 170MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2240IUP-12#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 638mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2240-12 is 210Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 2.79ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used if
the input clock has a non 50% duty cycle. This circuit uses
the rising edge of the ENC
The falling edge of ENC
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 40% to 60% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
V
THRESHOLD
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
= 1.5V
CLOCK
INPUT
+
is ignored and the internal falling
0.1μF
+
pin to sample the analog input.
0.1μF
0.1μF
1.5V
•
ETC1-1-13
ENC
ENC
MA/COM
T1
+
–
LTC2240-12
•
50Ω
50Ω
Figure 11. Transformer Driven ENC
224012 F12a
0.1μF
8.2pF
100Ω
ENC –
ENC
+
LTC2240-12
V
V
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
The lower limit of the LTC2240-12 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specifi ed minimum operating frequency
for the LTC2240-12 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overfl ow bit.
DD
DD
1.5V BIAS
1.5V BIAS
4.8k
4.8k
+
/ENC
CLOCK
V
LVDS
Figure 12b. ENC Drive Using LVDS
DD
–
DD
100Ω
or 2/3V
ADC CIRCUITS
0.1μF
0.1μF
TO INTERNAL
DD
ENC
ENC
224012 F11
using external resistors.
+
–
LTC2240-12
LTC2240-12
224012 F12b
19
224012fc