LTC2240IUP-12#PBF Linear Technology, LTC2240IUP-12#PBF Datasheet
LTC2240IUP-12#PBF
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LTC2240IUP-12#PBF Summary of contents
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... An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts. ...
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... REFHB 10 REFLA 11 REFLA 12 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL LTC2240CUP-12#PBF LTC2240CUP-12#TRPBF LTC2240IUP-12#PBF LTC2240IUP-12#TRPBF LEAD BASED FINISH TAPE AND REEL LTC2240CUP-12 LTC2240CUP-12#TR LTC2240IUP-12 LTC2240IUP-12#TR Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi label on the shipping container. ...
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CONVERTER CHARACTERISTICS temperature range, otherwise specifi cations are at T PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise ANALOG INPUT The l denotes the specifi cations which ...
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LTC2240-12 INTERNAL REFERENCE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance CM DIGITAL INPUTS AND DIGITAL OUTPUTS full operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER + – ...
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DIGITAL INPUTS AND DIGITAL OUTPUTS full operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER LOGIC OUTPUTS (LVDS MODE) V Differential Output Voltage OD V Output Common Mode Voltage OS POWER REQUIREMENTS range, otherwise specifi cations are at ...
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LTC2240-12 TIMING CHARACTERISTICS range, otherwise specifi cations are at T SYMBOL PARAMETER DATA to CLKOUT Skew Pipeline Latency Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent ...
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TYPICAL PERFORMANCE CHARACTERISTICS 8192 Point FFT 70MHz, IN –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) 224012 G04 ...
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LTC2240-12 TYPICAL PERFORMANCE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range 30MHz, –1dB, IN LVDS Mode 90 85 SFDR SNR 100 120 140 160 180 200 ...
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PIN FUNCTIONS (CMOS Mode (Pins 1, 2): Positive Differential Analog Input. IN – A (Pins 3, 4): Negative Differential Analog Input. IN REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip ...
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LTC2240-12 PIN FUNCTIONS (LVDS Mode) + AIN (Pins 1, 2): Positive Differential Analog Input. – AIN (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, ...
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FUNCTIONAL BLOCK DIAGRAM + A IN INPUT FIRST PIPELINED S/H ADC STAGE – 1.25V CM REFERENCE 2.2μF RANGE SELECT REF SENSE BUF SECOND PIPELINED THIRD PIPELINED ADC STAGE ADC STAGE REFH REFL INTERNAL CLOCK SIGNALS DIFFERENTIAL DIFF ...
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LTC2240-12 TIMING DIAGRAMS ANALOG INPUT – ENC + ENC D0-D11, OF – CLKOUT + CLKOUT ANALOG INPUT – ENC + ENC DA0-DA11, OFA CLKOUTB CLKOUTA DB0-DB11, OFB 12 LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels ...
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TIMING DIAGRAMS ANALOG INPUT – ENC + ENC DA0-DA11, OFA DB0-DB11, OFB CLKOUTB CLKOUTA Demultiplexed CMOS Outputs with Simultaneous Update ANALOG INPUT – ENC + ENC DA0-DA11, OFA DB0-DB11, OFB CLKOUTB CLKOUTA Demultiplexed CMOS Outputs with Interleaved Update All Outputs ...
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LTC2240-12 APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen- tal input frequency and the RMS amplitude of all other frequency components at ...
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APPLICATIONS INFORMATION Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifi er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input ...
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LTC2240-12 APPLICATIONS INFORMATION Input Drive Impedance As with all high performance, high speed ADCs, the dy- namic performance of the LTC2240-12 can be infl uenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input ...
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APPLICATIONS INFORMATION the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequen- cies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. + – The A and A ...
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LTC2240-12 APPLICATIONS INFORMATION LTC2240-12 2Ω 1.25V BANDGAP 1.25V 2.2μF RANGE DETECT AND CONTROL TIE TO V FOR 2V RANGE; DD SENSE TIE TO V FOR 1V RANGE; CM RANGE = 2 • V FOR SENSE REFLB 0.5V < ...
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APPLICATIONS INFORMATION MA/COM 0.1μF ETC1-1-13 CLOCK • INPUT 0.1μF ENC V = 1.5V THRESHOLD 1.5V ENC 0.1μF Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter Maximum and Minimum Encode Rates The maximum encode rate for the LTC2240-12 is ...
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LTC2240-12 APPLICATIONS INFORMATION Table 1. Output Codes vs Input Voltage + – A – A D11 – (2V Range) OF (Offset Binary) >+1.000000V 1 1111 1111 1111 +0.999512V 0 1111 1111 1111 +0.999024V 0 1111 1111 1110 ...
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APPLICATIONS INFORMATION LTC2240- DATA PREDRIVER FROM LOGIC LATCH OE Figure 13a. Digital Output Buffer in CMOS Mode Data Format The LTC2240-12 parallel digital output can be selected for offset binary or 2’s complement format. The format ...
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LTC2240-12 APPLICATIONS INFORMATION In the CMOS output mode any voltage up to 2.625V. OGND can be powered with any voltage from GND and must be less than OV The logic outputs will swing between OGND ...
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APPLICATIONS INFORMATION some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not fi lter the clock ...
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LTC2240-12 APPLICATIONS INFORMATION GND 16 GND 61 GND 64 GND ...
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APPLICATIONS INFORMATION Silkscreen Top Layer 1 Component Side LTC2240-12 Layer 2 GND Plane Layer 3 Power/Ground Plane 25 224012fc ...
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LTC2240-12 APPLICATIONS INFORMATION Layer 4 Power/Ground Planes Layer 5 Power/Ground Planes 26 Layer Back Solder Side Silk Screen Back, Solder Side 224012fc ...
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... SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. UP Package 64-Lead Plastic QFN (9mm × ...
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... High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz 12.5dB, 50Ω Single-Ended RF and LO Ports www.linear.com ● 224012fc LT 0809 REV C • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2006 ...