AD7942BRMZ Analog Devices Inc, AD7942BRMZ Datasheet - Page 6

• Manufacturer Part Number: AD7942BRMZ
• Description: IC ADC 14BIT 250KSPS 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7942BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 1.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 14bit
• Sampling Rate: 250kSPS
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analog: 2.3V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7942CB - BOARD EVALUATION FOR AD7942
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7942
VDD = 2.3 V to 4.5 V
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
Timing Diagrams
See Figure 2 and Figure 3 for load conditions.
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
1
, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, T
30% VIO
NOTES
1
2
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
t
DELAY
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Reference Levels for Timing
TO SDO
2V OR VIO – 0.5V
0.8V OR 0.5V
50pF
C
L
Rev. B | Page 6 of 24
500µA
500µA
2
1
I
I
OL
OH
70% VIO
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
1.4V
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
SCKL
SCKH
HSDO
DSDO
EN
DIS
SSDICNV
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
1
Min
0.7
1.8
5
10
25
29
35
40
12
12
5
30
0
5
8
5
4
A
= −40°C to +85°C.
Typ
Max
3.2
24
30
35
18
22
25
36
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns