AD7730LBRU Analog Devices Inc, AD7730LBRU Datasheet - Page 8

• Manufacturer Part Number: AD7730LBRU
• Description: IC ADC TRANSDUCER BRIDGE 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7730LBRU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 600
• Data Interface: DSP, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• For Use With: EVAL-AD7730LEBZ - BOARD EVALUATION FOR AD7730EVAL-AD7730EBZ - BOARD EVAL FOR AD7730

Pin
No.
10
11
12
13
14
15
16
17
AD7730/AD7730L
3
4
5
6
7
8
9
Mnemonic
MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
POL
SYNC
RESET
V
AGND
AV
AIN1(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
REF IN(+)
REF IN(–)
ACX
ACX
BIAS
DD
Analog Input Channel 1. Negative input of the differential, programmable gain primary analog input pair.
Analog Input Channel 2 or Digital Output 1. This pin can be used either as part of a second analog input
Function
and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig-
nal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving
one CMOS load. If the user does not require it, MCLK OUT can be turned off with the CLKDIS bit of the Mode
Register. This ensures that the part is not burning unnecessary power driving capacitance on the MCLK OUT pin.
Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces-
sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7730 puts out data on the
DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA
IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial
clock (such as most microcontroller applications), this means that the serial clock should idle low between
data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high.
In this mode, the AD7730 puts out data on the DATA OUT line in a read operation on a high-to-low transi-
tion of SCLK and clocks in data from the DATA IN line in a write operation on a low-to-high transition of
SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this
means that the serial clock should idle high between data transfers.
Logic Input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7730s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration
control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital
interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up
for a subsequent operation which will commence when the SYNC pin is deasserted.
Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and
all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock
oscillator is reset when the RESET pin is exercised.
Analog Output. This analog output is an internally-generated voltage used as an internal operating bias point.
This output is not for use external to the AD7730 and it is recommended that the user does not connect any-
thing to this pin.
Ground reference point for analog circuitry.
Analog Positive Supply Voltage. The AV
Analog Input Channel 1. Positive input of the differential, programmable-gain primary analog input pair. The
differential analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV
in unipolar mode, and 10 mV, 20 mV, 40 mV and 80 mV in bipolar mode.
channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an
analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. The
analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipo-
lar mode and 10 mV, 20 mV, 40 mV and 80 mV in bipolar mode. When selected as a digital output,
this output can programmed over the serial interface using bit D1 of the Mode Register.
Analog Input Channel 2 or Digital Output 0. This pin can be used either as part of a second analog input channel
or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it
is the negative input of the differential, programmable-gain secondary analog input pair. When selected as a digital
output, this output can programmed over the serial interface using bit D0 of the Mode Register.
Reference Input. Positive terminal of the differential reference input to the AD7730. REF IN(+) can lie
anywhere between AV
IN(+) and REF IN(–)) should be +5 V when the HIREF bit of the Mode Register is 1 and +2.5 V when the
HIREF bit of the Mode Register is 0.
Reference Input. Negative terminal of the differential reference input to the AD7730. The REF IN(–) poten-
tial can lie anywhere between AV
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-
excited bridge applications. When ACX is high, the bridge excitation is taken as normal and when ACX is
low, the bridge excitation is reversed (chopped). If AC = 0 (ac mode turned off) or CHP = 0 (chop mode
turned off), the ACX output remains high.
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-
excited bridge applications. This output is the complement of ACX. In ac mode, this means that it toggles in
anti-phase with ACX . If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the ACX output
remains low. When toggling, it is guaranteed to be nonoverlapping with ACX. The non-overlap interval, when
both ACX and ACX are low, is one master clock cycle.
DD
and AGND. The nominal reference voltage (the differential voltage between REF
DD
and AGND.
DD
–8–
to AGND differential is 5 V nominal.
REV. A