AD9225ARS Analog Devices Inc, AD9225ARS Datasheet - Page 18

• Manufacturer Part Number: AD9225ARS
• Description: IC ADC 12BIT 25MSPS 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9225ARS

• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Parallel
• Number Of Converters: 7
• Power Dissipation (max): 373mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• No. Of Channels: 2
• Interface Type: Parallel
• For Use With: AD9225-EB - BOARD EVAL FOR AD9225
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9225
Digital Output Driver Considerations (DRVDD)
The AD9225 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V,
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. However,
large drive currents tend to cause glitches on the supplies and may
affect SINAD performance. Applications requiring the ADC to
drive large capacitive loads or large fanout may require additional
decoupling capacitors on DRVDD. In extreme cases, external
buffers or latches may be required.
Clock Input and Considerations
The AD9225 internal timing uses the two edges of the clock input
to generate a variety of internal timing signals. The clock input
must meet or exceed the minimum specified pulse width high and
low (t
the Switching Specifications table to meet the rated performance
specifications. For example, the clock input to the AD9225 operat-
ing at 25 MSPS may have a duty cycle between 45% to 55% to
meet this timing requirement since the minimum specified t
t
this range to the extent that both t
All high speed high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale input
frequency (f
with the following equation:
In the equation, the rms aperture jitter, t
sum square of all the jitter sources, which include the clock
input, analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
Clock input should be treated as an analog signal in cases where
aperture jitter may affect the dynamic range of the AD9225. Power
supplies for clock drivers should be separated from the ADC out-
put driver supplies to avoid modulating the clock signal with digital
noise. Low jitter crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or other method), it should be retimed by the
original clock at the last step.
The clock input is referred to as the analog supply. Its logic thresh-
old is AVDD/2. If the clock is being generated by 3 V logic, it will
have to be level shifted into 5 V CMOS logic levels. This can also
be accomplished by ac coupling and level-shifting the clock signal.
CL
is 18 ns. For low clock rates, the duty cycle may deviate from
CH
and t
Figure 23. Overrange or Underrange Logic
MSB
MSB
OTR
OTR
0
0
1
1
IN
) due to only aperture jitter (t
CL
Table V. Out-of-Range Truth Table
) specifications for the given ADC as defined in
SNR = 20 log
MSB
0
1
0
1
CH
10
È
Í
Î
and t
2p f
Analog Input Is
In Range
In Range
Underrange
Overrange
A
1
, represents the root-
IN
CL
A
) can be calculated
t
are satisfied.
A
˘
˙
˚
OVER = “1”
UNDER = “1”
CH
and
–18–
The AD9225 has a clock tolerance of 5% at 25 MHz. One way to
obtain a 50% duty cycle clock is to divide down a clock of higher
frequency, as shown in Figure 24. This configuration will also
decrease the jitter of the source clock.
In this case, a 50 MHz clock is divided by two to produce the
25 MHz clock input for the AD9225. In this configuration, the
duty cycle of the 50 MHz clock is irrelevant.
The input circuitry for the CLOCK pin is designed to accommo-
date CMOS inputs. The quality of the logic input, particularly
the rising edge, is critical in realizing the best possible jitter
performance of the part; the faster the rising edge, the better
the jitter performance.
As a result, careful selection of the logic family for the clock driver,
as well as the fanout and capacitive load on the clock line, is impor-
tant. Jitter-induced errors become more predominant at higher
frequency and large amplitude inputs, where the input slew rate
is greatest.
Most of the power dissipated by the AD9225 is from the analog
power supplies. However, lower clock speeds will reduce digital
current. Figure 25 shows the relationship between power and
clock rate.
Direct IF Down Conversion Using the AD9225
Sampling IF signals above an ADC’s baseband region (i.e.,
dc to f
applications. This process is often referred to as direct IF down
conversion or undersampling. There are several potential benefits
in using the ADC to alias (i.e., or mix) down a narrowband or
wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated baseband amplifiers and
filters, reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as filter-
ing, channel selection, quadrature demodulation, data reduction,
S
/2) is becoming increasingly popular in communication
Figure 25. Power Consumption vs. Clock Rate
380
360
340
320
300
280
260
240
220
200
180
0
Figure 24. Divide-by-Two Clock Circuit
50MHz
5
10
REFERENCE
INTERNAL
D
2V
SAMPLE RATE
15
+5V
+5V
R
S
REFERENCE
Q
Q
INTERNAL
20
1V
25
25MHz
30
Rev. C
35