AD7476AYRM Analog Devices Inc, AD7476AYRM Datasheet - Page 21

• Manufacturer Part Number: AD7476AYRM
• Description: IC ADC 12BIT 2.35V 1MSPS 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7476AYRM

• Rohs Status: RoHS non-compliant
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A

SERIAL INTERFACE
Figure 24, Figure 25, and Figure 26 show the detailed timing
diagrams for serial interfacing to the AD7476A, AD7477A, and
AD7478A, respectively. The serial clock provides the conversion
clock and also controls the transfer of information from the
AD7476A/AD7477A/AD7478A during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 24 at Point B. On the 16th SCLK falling edge,
the SDATA line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
SDATA
SCLK
THREE-STATE
SDATA
THREE-STATE
SDATA
SCLK
CS
SCLK
CS
CS
THREE-
STATE
t
2
t
Z
2
t
Z
2
1
Z
t
3
1
t
3
1
t
ZERO
ZERO
3
ZERO
4 LEADING ZEROS
4 LEADING ZEROS
4 LEADING ZEROS
2
2
2
ZERO
ZERO
ZERO
t
CONVERT
3
3
3
ZERO
ZERO
t
ZERO
4
t
6
Figure 24. AD7476A Serial Interface Timing Diagram
Figure 25. AD7477A Serial Interface Timing Diagram
Figure 26. AD7478A Serial Interface Timing Diagram
4
4
4
DB11
t
CONVERT
DB7
DB9
t
t
t
4
4
6
t
6
5
11
t
CONVERT
5
t
DB10
7
t
B
DB8
7
t
Rev. F | Page 21 of 28
7
12
1/THROUGHPUT
ZERO
1/ THROUGHPUT
1/ THROUGHPUT
13
13
13
B
DB2
DB0
4 TRAILING ZEROS
ZERO
falling edge, as shown in Figure 24. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476A.
For the AD7477A, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next rising edge as shown
at Point B in Figure 25. If the rising edge of CS occurs before
14 SCLKs have elapsed, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, SDATA returns to three-state on the
16th SCLK falling edge, as shown in Figure 25.
For the AD7478A, the conversion requires 12 SCLK cycles to
complete. The track-and-hold goes back into track on the rising
edge after the 11th falling edge, as shown in Figure 26 at Point B. If
the rising edge of CS occurs before 12 SCLKs have elapsed, the
conversion is terminated and the SDATA line goes back into three-
state. If 16 SCLKs are considered in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 26.
B
14
t
5
14
t
14
t
5
DB1
2 TRAILING ZEROS
5
ZERO
ZERO
15
15
15
DB0
ZERO
t
8
ZERO
AD7476A/AD7477A/AD7478A
t
16
8
16
t
16
8
THREE-STATE
THREE-STATE
THREE-STATE
t
QUIET
t
QUIET
t
t
QUIET
1
t
1
t
1