AD7476AYRM Analog Devices Inc, AD7476AYRM Datasheet - Page 9

• Manufacturer Part Number: AD7476AYRM
• Description: IC ADC 12BIT 2.35V 1MSPS 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7476AYRM

• Rohs Status: RoHS non-compliant
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A

Timing Diagrams
Timing Example 1
Having f
time of
where:
t
requirement of 250 ns for t
From Figure 4, t
where:
t
satisfying the minimum requirement of 50 ns.
2
8
= 36 ns maximum. This allows a value of 204 ns for t
= 10 ns min, leaving t
t
2.5 (1/f
2
Figure 2. Load Circuit for Digital Output Timing Specifications
+ 12.5 (1/f
SDATA
SCLK
SCLK
SCLK
CS
CS
TO OUTPUT
SCLK
= 20 MHz and a throughput of 1 MSPS, a cycle
THREE-
) + t
STATE
ACQ
SCLK
PIN
is comprised of
8
) + t
+ t
t
t
2
50pF
2
Z
ACQ
QUIET
C
1
1
ACQ
t
L
3
ZERO
ACQ
to be 365 ns. This 365 ns satisfies the
4 LEADING ZEROS
= 1 µs
200 µ A
200 µ A
.
2
2
ZERO
I
I
OL
OH
3
3
ZERO
t
4
12.5(1/f
1.6V
4
Figure 3. AD7476A Serial Interface Timing Diagram
4
SCLK
DB11
t
Figure 4. Serial Interface Timing Example
t
6
)
CONVERT
QUIET
5
t
5
CONVERT
t
DB10
7
,
Rev. F | Page 9 of 28
1/THROUGHPUT
13
13
B
B
DB2
Timing Example 2
Having f
cycle time of
where:
t
the requirement of 250 ns for t
From Figure 4, t
This allows a value of 128 ns for t
requirement of 50 ns.
In this example and with other, slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 50 ns minimum t
conversions. In Example 2, acquire the signal fully at
approximately Point C in Figure 4.
2
= 10 ns min, this leaves t
14
t
2.5 (1/f
14
t
2
5
+ 12.5 (1/f
DB1
SCLK
C
SCLK
= 5 MHz and a throughput is 315 kSPS yields a
15
15
) + t
ACQ
DB0
SCLK
t
AD7476A/AD7477A/AD7478A
is comprised of
8
ACQ
16
) + t
t
+ t
16
8
QUIET
ACQ
t
8
THREE-STATE
ACQ
, t
= 3.174 µs
8
to be 664 ns. This 664 ns satisfies
ACQ
= 36 ns maximum
t
t
.
QUIET
QUIET
QUIET
t
1
, satisfying the minimum
QUIET
between