AD6600AST Analog Devices Inc, AD6600AST Datasheet
AD6600AST
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AD6600AST Summary of contents
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PRODUCT DESCRIPTION The AD6600 mixed-signal receiver chip directly samples signals at analog input frequencies up to 250 MHz. The device includes 0dB, –12dB, –24dB AIN ATTEN AIN DETECT SET PEAK RSSI BIN ATTEN BIN 0dB, –12dB, –24dB A_SEL two ...
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... C unless otherwise noted.) MAX AD6600AST Min Typ Max CMOS 2.8 DVCC – 0.2 0.2 0.5 4.0 DVCC – 0.35 0.35 0.5 Two’s Complement 2.8 DVCC – 0.2 ...
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... Full V CLK2×_2 t Full V CLK2×L Full V Full V Full V Full V Full V Full V ; these specifications are shown in the data tables and timing diagrams. Encode duty cycle ENCH AD6600 1 AD6600AST Min Typ Max Unit 1/(t ) MSPS ENC 20 MSPS 6 MSPS 0.3 ps rms 2× f MSPS ...
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... Full IV H_AEN Full IV Full Full IV EN_AFL 4 t Full IV S_AEN Full IV 6 25°C IV Full +85 C unless otherwise noted.) MAX AD6600AST Min Typ Max 6.5 8.0 9 )/2 CF ENCH 25.7 27.2 28.7 19.0 20.5 22.0 3.0 6.5 3.0 6.5 10.0 15.0 20.0 11.0 15.5 22 ...
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... IV 25°C IV 25°C V 25°C IV 25°C IV 25° – +85 C unless MIN MAX AD6600AST Min Typ Max 450 2.45 2.57 2.62 2.86 197–j24 188–j48 175–j57 161–j67 151–j73 140–j80 141–j75 173–j107 5 ...
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... Full V Full V Full V Full V Full V Full V Full V Full V Full V Full V 25° Full V 25° Full V Full V Full V Full V Full V Full IV 28 AD6600AST Typ Max Unit 57 ± 53 ± dBc 68 dBc 68 ± 6 dBc 60 dBc 59 dBc 67 ± 6 dBc 60 dBc 56 dBc 55 dBc 65 ± ...
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... Level Min Full V Full V Full V Full V Full V Full V 25° Full V 25° Full V Full V Full V Full V AD6600 AD6600AST Typ Max Unit 74.5 dBc 71 dBc 68 ± 6 dBc 67 dBc 65 dBc 67 ± 6 dBc 67 dBc 66 dBc 66 dBc 65 ± 6 dBc 66.5 dBc 65 dBc 65 ± 6 dBc ...
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... AVCC V Model °C –40 +85 °C 150 AD6600AST °C 300 °C AD6600ST/PCB = 16°C/W, θ = 55°C/W. JA ORDERING GUIDE Temperature Package Package Range Description Option –40°C to 44-Terminal LQFP ST-44 +85°C (Low-Profile Quad (Ambient) Plastic Flatpack) Evaluation Board with AD6600AST WARNING! ESD SENSITIVE DEVICE ...
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Pin Number Name 1, 33 DVCC 2, 5, 13, 19, 21, 24, 30, 32 GND 14, 15, 18, 20, 25, 31 AVCC 6–8 RSSI[2: B_SEL, A_SEL 11 AIN AIN 12 FLT, FLT 16, 17 BIN ...
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AD6600 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. The bandwidth is determined by the internal track-and-hold when the ...
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RSSI Gain Step The input amplitude span between taps of the RSSI (received signal strength) attenuator ladder. Ideally each stage should span input power. RSSI Hysteresis The amount of movement in the RSSI switch points, depending on ...
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AD6600 EQUIVALENT CIRCUITS ATTENUATOR STAGE AVCC EQUIVALENT INPUT R SHOWN ONLY AIN 100 V REF GND BUF AVCC 100 AIN GND AVCC ISEL_A ISEL_B AVCC A_SEL BIAS GND GND DVCC CURRENT MIRROR DVCC V REF 500 CURRENT MIRROR AVCC GND ...
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AD6600 TIMING DIAGRAMS t ENCH ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 1_DRL D [10:0] RSSI [2:0] AB_OUT t ENCH ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 2 D [10:0] RSSI ...
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AD6600 t ENCH ENCODE ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 2 t H_DEN D [10:0] RSSI [2:0] t H_AEN AB_OUT CLK2 D [10:0] RSSI [2:0] AB_OUT 20 ENCODE 40 CLK2 ENCODE 8 CLK2 t ...
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AIN ATTEN AIN DETECT SET PEAK RSSI BIN ATTEN BIN 0dB, –12dB, –24dB A_SEL B_SEL THEORY OF OPERATION The AD6600, dual-channel, gain-ranging ADC integrates ana- log IF circuitry with high speed data conversion. Each analog input stage ...
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AD6600 Table I. Attenuator and Gain Settings Attenuator Gain Amp Total 0 dB + +12 dB +12 dB – – –24 dB +18 dB –6 ...
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Table II. Selecting AD6600 Operating Mode Output vs. Encode Clock Mode A_SEL B_SEL n Dual: A Single Single Not Valid 0 0 – A_SEL and B_SEL are not logic ...
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AD6600 If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown in Figure 19. VT 0.1 F ENCODE ECL/ PECL 0.1 F ENCODE VT Driving the ...
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AVCC 315 315 FROM GAIN STAGE ENCODE GND × × Figure 24 shows why settling is important for this circuit. If the 4×/8× amp does not settle (come out of clamp), the amplitude presented to the ADC will be decreased. ...
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... Ceramic Chip Capacitor 1206, 0.1 µF Tantalum Chip Capacitor, 10 µF Ceramic Chip Capacitor 0805, 0.1 µF Ceramic Chip Capacitor 0508, 0.1 µF 1N2810 Schottky Diode AD6600AST 20-Pin Double Row Male Header 50-Pin Double Row Male Header, Right Angle Omitted Surface Mount Resistor 1206, 10 kΩ ...
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BIN D0 D1 GND D2 AVCC D3 GND D4 AVCC D5 FLT FLT D6 D7 AVCC D8 AVCC D9 GND D10 AIN (MSB) AD6600 GND VCC GND VCC VCC VCC GND ...
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AD6600 ...
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Connecting the AD6600 with the AD6620 The AD6600 interfaces directly to the AD6620 Digital Receive Signal Processor as shown in Figure 31. No additional external components are required. Note that the layout requirements dis- cussed previously do apply and deviations ...
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AD6600 44-Terminal LQFP (Low-Profile Quad Plastic Flatpack) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). (ST-44) 0.063 (1.60) MAX 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN 0.006 (0.15) 0.002 (0.05) ...