AD7660ACP Analog Devices Inc, AD7660ACP Datasheet
AD7660ACP
Specifications of AD7660ACP
Related parts for AD7660ACP
AD7660ACP Summary of contents
Page 1
FEATURES Throughput: 100 kSPS INL: 3 LSB Max ( 0.0046% of Full-Scale) 16-Bit Resolution with No Missing Codes S/(N+D Min @ 10 kHz Typ @ 45 kHz THD: –96 dB Max @ 10 kHz Analog ...
Page 2
AD7660–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes 2 Transition Noise 3 Full-Scale Error ...
Page 3
Parameter TEMPERATURE RANGE Specified Performance NOTES LSB means least significant bit. With the 2.5 V input range, one LSB is 38.15 mV Typical rms noise at worst-case transitions and temperatures. 3 See Definition of Specifications ...
Page 4
... SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 1. Load Circuit for Digital Interface Timing Model AD7660AST AD7660ASTRL AD7660ACP AD7660ACPRL 1 EVAL-AD7660CB EVAL-CONTROL BRD2 NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows control and communicate with all Analog Devices evaluation boards ending in the CB designators ...
Page 5
Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally Connect 40–42, 44–48 4 DGND DI Must Be Tied to Digital Ground 5 ...
Page 6
AD7660 Pin No. Mnemonic Type Description 22 D9 DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, ...
Page 7
DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB before ...
Page 8
Performance Characteristics AD7660 –1 –2 –3 0 16384 32768 49152 65536 CODE TPC 1. Integral Nonlinearity vs. Code 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 16384 32768 49152 65536 ...
Page 9
SNR 90 15.0 S/(N+D) ENOB 14 14.0 75 13.5 13 100 1k FREQUENCY – Hz TPC 10. SNR, S/(N+D), and ENOB vs. Frequency 10M AVDD 1M DVDD 100k 10k OVDD 1k ...
Page 10
AD7660 CIRCUIT INFORMATION The AD7660 is a fast, low power, single-supply, precise 16-bit analog-to-digital converter (ADC). The AD7660 is capable of converting 100,000 samples per second (100 kSPS) and allows power saving between conversions. When operating at 100 SPS, for ...
Page 11
Transfer Functions Using the OB/2C digital input, the AD7660 offers two output codings: straight binary and twos complement. The LSB size is /65536, which is about 38.15 mV. The ideal transfer charac- V REF teristic for the AD7660 is shown ...
Page 12
AD7660 Analog Input Figure 6 shows an equivalent circuit of the input structure of the AD7660. AVDD INGND C1 D2 AGND Figure 6. Equivalent Analog Input Circuit The two diodes D1 and D2 provide ESD protection for ...
Page 13
The AD8519, OP162, or the OP184 meet these requirements and are usually appropriate for almost all applications alternative, in very high speed and noise-sensitive applications, the AD8021 with an external compensation capacitor the AD829 ...
Page 14
AD7660 CONVERSION CONTROL Figure 11 shows the detailed timing diagrams of the conversion process. The AD7660 is controlled by the signal CNVST, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until ...
Page 15
CNVST, RD BUSY t 3 PREVIOUS DATA BUS CONVERSION Figure 15. Slave Parallel Data Timing for Reading (Read during Convert) CS CNVST BUSY t 29 SYNC t 14 ...
Page 16
AD7660 CS BUSY SCLK t 31 SDOUT t 16 SDIN t 33 Figure 18. Slave Serial Data Timing for Reading (Read after Convert) Usually, because the AD7660 has a longer acquisition phase than the conversion phase, the data is read ...
Page 17
CS CNVST BUSY t 3 SCLK t 31 SDOUT t 16 Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) External Clock Data Read during Conversion Figure 20 shows the detailed timing diagrams of this method. ...
Page 18
AD7660 APPLICATION HINTS Bipolar and Wider Input Ranges In some applications desired to use a bipolar or wider analog input range like, for instance, ± ± Although the ...
Page 19
SEATING 0.05 PLANE ROTATED 90 CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12 MAX 0.85 0.80 SEATING PLANE REV. D OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown ...
Page 20
AD7660 Revision History Location 10/03—Data Sheet changed from REV REV. D. Update format . . . . . . . . . . . . . . . . . . . . . . . . . ...