AD7663ASTRL Analog Devices Inc, AD7663ASTRL Datasheet - Page 3

• Manufacturer Part Number: AD7663ASTRL
• Description: IC ADC 16BIT CMOS 5V 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7663ASTRL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 41mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: EVAL-AD7663CBZ - BOARD EVALUATION FOR AD7663

Parameter
TEMPERATURE RANGE
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
Input Voltage
Range
±4 REF
±2 REF
±REF
0 V to 4 REF
0 V to 2 REF
0 V to REF
NOTES
1
2
3
TIMING SPECIFICATIONS
Parameter
Refer to Figures 11 and 12
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
Refer to Figures 17 and 18 (Master Serial Interface Modes)
REV. B
LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV.
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
Tested in Parallel Reading Mode.
Tested with the 0 V to 5 V range and V
With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
Contact factory for extended temperature range.
Typical analog input impedance.
With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
For this range the input is high impedance.
Specified Performance
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay (Read during Convert)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
Internal SCLK LOW
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
Master Serial Read after Convert Mode
2
2
2
2
8
IND(4R)
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
2
2
IN
– V
2
INGND
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
= 0 V. See Power Dissipation section.
Conditions
T
2
MIN
Table I. Analog Input Configuration
to T
INC(4R)
INGND
V
V
V
V
V
IN
IN
IN
IN
IN
MAX
1
–3–
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
INB(2R)
INGND
INGND
V
INGND
V
V
Min
–40
IN
IN
IN
Min
5
4
10
2.75
10
20
5
4
25
15
9.5
4.5
2
3
Typ
Typ
2
0.5
INA(R)
REF
REF
REF
INGND
INGND
V
IN
Max
+85
Max
30
1.25
1.25
1.25
40
15
10
10
10
40
Input
Impedance
5.85 kW
3.41 kW
2.56 kW
3.41 kW
2.56 kW
Note 3
AD7663
Unit
°C
Unit
ns
µs
ns
µs
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
1