AD9218BST-RL80 Analog Devices Inc, AD9218BST-RL80 Datasheet - Page 8

• Manufacturer Part Number: AD9218BST-RL80
• Description: IC ADC 10BIT DUAL 80MSPS 48LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9218BST-RL80

• Rohs Status: RoHS non-compliant
• Number Of Bits: 10
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 525mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP

AD9218
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
V
Analog Inputs
Digital Inputs
REF
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
θ
solid ground plane)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
A
D
, V
(measured on a 4-layer board with
IN
DD
Inputs
Rating
4 V
–0.5 V to V
–0.5 V to V + 0.5 V
–0.5 V to V
20 mA
–55°C to +125°C
–65°C to +150°C
150°C
150°C
57°C/W
D
DD
D
+ 0.5 V
+ 0.5 V
Rev. C | Page 8 of 28
EXPLANATION OF TEST LEVELS
I.
II.
III.
IV.
V.
VI.
Table 6. User Select Modes
S1
0
0
1
1
ESD CAUTION
S2
0
1
0
1
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design
and characterization testing for industrial temperature
range.
100% production tested at temperature extremes for
military devices.
Power-Down and Data Alignment Settings
Power down both Channel A and Channel B.
Power down Channel B only.
Normal operation (data align disabled).
Data align enabled (data from both channels
available on rising edge of Clock A. Channel B data is
delayed by a ½ clock cycle.)