CS5516-ASZ Cirrus Logic Inc, CS5516-ASZ Datasheet - Page 15

• Manufacturer Part Number: CS5516-ASZ
• Description: IC ADC 16BIT BRIDGE TRAS 24-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5516-ASZ

• Number Of Bits: 16
• Sampling Rate (per Second): 60
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 37.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1101-5

which calibration is initiated is common to each
of the calibration registers. The configuration
register controls the execution of the calibration
process. Bits CC3--CC0 in the configuration
register determine which type of calibration will
be performed and which of the five calibration
registers will be affected. On the falling edge of
the 24th SCLK, the configuration word will be
latched into the configuration register and the se-
lected calibration will be executed. The time
required to perform a calibration is listed in Ta-
ble 3. The DRDY pin will remain a logic 1
during calibration, and will go low when the
calibration step is completed.
The serial port should not be accessed while a
calibration is in progress. The EC bit of the
configuration register remains a logic 1 until it is
overwritten by a new configuration word (EC =
0). Consequently, if EC is left active, any write
(the falling edge of the 24th SCLK) to any regis-
ter inside the converter will cause a re-execution
of the calibration sequence. This occurs because
the internal microcontroller executes the contents
of the configuration register every time the 24th
SCLK falls after writing a 24-bit word to any
internal register. To be certain that calibrations
will not be re-executed each time a new word is
written or read via the serial port, the EC bit of
the configuration register must be written back
to a logic 0 after the final calibration step has
been completed.
The CC3--CC0 bits of the configuration register
determine the type of calibration to be per-
DS74F1
DS74F2
DRDY remains high through calibration sequence. In all modes, DRDY falls immediately upon completion of the calibration
sequence.
EC
1
1
1
1
1
0
CC3
Configuration Register
1
0
0
0
1
X
CC2
X
0
1
0
0
1
CC1
Table 3. CS5516/CS5520 Calibration Control
X
0
0
1
0
0
CC0
X
0
0
0
1
0
VREF & AIN Non-ratiometric Offset
formed. The calibration steps should be per-
formed in the following sequence. If the user
determines that non-ratiometric offset calibra-
tion is important, the non-ratiometric offset
errors of the VREF and AIN input channels
should be calibrated first. Then the ratiometric
offset of the AIN channel should be calibrated.
And finally, the AIN channel gain should be
calibrated.
Non-ratiometric Errors
To calibrate out the VREF and AIN
non-ratiometric errors, the input channels to the
VREF path into the converter and the AIN path
into the converter must be grounded (this may
occur at the pins of the IC, or at the bridge exci-
tation as shown in Figure 3.). Then the EC,
CC2 and CC3 bits of the configuration register
must be set to logic 1. The converter will then
perform a non-ratiometric calibration and place
VREF Non-ratiometric Offset
AIN Non-ratiometric Offset
Figure 3. Non-ratiometric System Calibration using
AIN Ratiometric Offset
AIN System Gain
End Calibration
CAL Type
*Note: The bridge can be grounded with a
CS5516
CS5520
relay or with jumpers to perform
non-ratiometric calibration.
Internal Excitation
VREF+
VREF-
AIN+
AIN-
BX1
BX2
+
CS5516, CS5520
1B*
Calibration Time
-
2,211,840/fclk
573,440/fclk
573,440/fclk
573,440/fclk
573,440/fclk
1A*
-
15
15